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20110301151907
- ：为解决现有视频监控系统中目标检测算法无法应付复杂的室外环境且计算量和存储量较大等问题，将像素从RGB 空间转换到YUV 空间建立基于码本的背景模型，并单独对每个码字中的亮度分量进行高斯建模，提取运动目标的轮廓后，用连通区域算法对图像进行形态 学处理。典型测试序列和ROC 数据的对比实验结果证明该算法是高效和实用的，且易于在DSP 或FPGA 等嵌入式系统上实时实现。-】In order to solve the problems that the existing motion det
UART_TX
- 通过FPGA串口发送到电脑的 HELLO WORLD 程序，成功调试，可以下载到板子上运行-This can sending the HELLO WORLD through the FPGA to computer ,you can launch the code on your board.
USB2_36M
- USB的驱动程序，能直接使用于FPGA与上位机USB接口的连接-USB driver, can be directly used in FPGA and USB PC interface
vhdl_fir
- 这是一个vhdl语言写的fir filter，包括receiver, filter, transfer,可用于驱动fpga等板子-this is a fir filter use VHDL language, include receiver, filter, transfer. can be used to drive fpga and some else boards
VHDL
- 基于FPGA的IIR滤波器的各模块VHDL程序- such as in science and project technique. Compared with FIR digital filter, IIR digital filter can get high selectivity with low factorial.
can_latest.tar
- CAN controller implimentation using HDL on fpga.SJA1000 chip was taken as refference.
zzlB
- QUARTUSII 9.0 下的三级流水线中值滤波工程，vhdl源程序等。可用于fpga做图像预处理。-the three stage pipeline median filter project under QUARTUSII 9 , VHDL source program. which can be used by FPGA to do image preprocessing.
dpsk_m_fpga
- 能够进行FPGA实现的DQPSK仿真程序！ -The DQPSK simulation program which can be implemented in FPGA.
linedet
- Program matlab describe line detection algorithm, we can use System Generator Tool with matlab to implement it in FPGA.
DDS_fir
- FFR滤波器在FPGA上的硬件实现，及检测！可以检测AD输入模块的滤波状况-FFR filter FPGA realize, can detect AD input data filtering effect
vga_DMA
- VGA的的检测，VGA的驱动及其测试模块！-vga FPGA realize, can detect AD input data filtering effect
uart_1203_4
- MUC+fpga 串口扩展，已调试通过，4路串口共用中断，收发fifo，波特率可调，其他的可以自己添加，网上类似资料极少，极具参考价值！只提供verilog源码！-MUC+ fpga McU.that, already debugging, through, 4 road serial common interrupt, receiving and dispatching fifo, baud rate can be adjusted, the other can add your own, o
decoder
- This paper put forward a pseudorandom sequence coder and decoder design scheme based on FPGA technology, in order to simulate the process of SSC (Spread Spectrum Communication). This scheme can be used as a didactical method to introduce SSC techno
CRC
- 在CPLD 或者ＦＰＧＡ中实现CRC,可以查找表方式或根据原理去实现-CPLD or FPGA CRC can lookup table according to the principle
All-DigitalQPSK-Demodulator
- Altem公司quartus II 8．1开发环境下，完成了中频全数字解调器的FPGA实现，并对数 字下变频、载波同步、位同步等解调器的核心模块设计进行了详细的分析和说明，给出 了实现框图和仿真波形。同时在本设计中应用了Altera公司的NiosII软核处理器技术， 用于载波的大频偏校正和解调器各个部分的监测和控制。最后给出了QPSK中频全数字 解调器关键性能指标的测试方法和测试结果，测试结果表明本设计达到了预期的性能指 标要求。-The Algorithm is con
jianpancaomiao
- 经过对系统做需求分析，详细功能设计、编码，模块连接，并利用FPGA实现相应的功能，经过波形仿真、下载调试，验证了设计方案的可行性及实现方法的有效性，基本实现了系统的要求。-Microwave controller system is a utility-type system that includes not only the function of simple operation, but also good effect of cook. According to fixed routi
FPGA_27demos
- 基于fpga的一些基本实例，实用性高，模块可直接应用-Some of the basic instance based on fpga, practicability, module can be used directly
fpgadev
- fpga的一个简单但实用的例程可以帮助你 学习fpga，深入了解相关编程语言-this is a example for using fpga，you can use it to understand the method
dds1
- 用ALTERA 公司的fpga芯片，编程语言是VerilogHDL,实现DDS数字信号发生器，可以产生正弦信号，三角信号，矩形信号。-ALTERA company fpga chip, programming languages, Verilog HDL, to achieve the DDS digital signal generator, can generate sine signal, triangle signal, rectangular signal
clock
- 用FPGA实现的电子钟代码，可实现年、月、日、时、分、秒计时及整点报时功能，可以手动设置时间-FPGA implementation of the electronic clock code, year, month, day, hours, minutes, seconds, chronograph, and the whole hour, you can manually set the time