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EDAshuzhizhong
- 设计一个能进行时、分、秒计时的十二小时制或二十四小时制的数字钟,并具有定时与闹钟功能,能在设定的时间发出闹铃音,能非常方便地对小时、分钟和秒进行手动调节以校准时间,每逢整点,产生报时音报时。实验平台: 1. 一台PC机; 2. MAX+PLUSII10.1。 Verilog HDL语言实现-The design of a can be hours, minutes, seconds time of 12 hours or 24 hours system, digital clock, and h
pcisim.tar
- 此代码用于生成测试PCI设备的Verilog代码(Verilog代码为一种硬件描述语言)。此代码可以直接运行于LINUX下。-This code used to generate test PCI devices Verilog code (Verilog code for a hardware descr iption language). This code can be directly under the running on LINUX.
a_block_with_several_functions_with_Verilog_HDL.ra
- Verilog是广泛应用的硬件描述语言,可以用在硬件设计流程的建模、综合和模拟等多个阶段。随着硬件设计规模的不断扩大,应用硬件描述语言进行描述的CPLD结构,成为设计专用集成电路和其他集成电路的主流。通过应用Verilog HDL对多功能电子钟的设计,达到对Verilog HDL的理解,同时对CPLD器件进行简要了解。 本文的研究内容包括: 对Altera公司Flex 10K系列的EPF10K 10简要介绍,Altera公司软件Max+plusⅡ简要介绍和应用Verilog HDL对多功能
FREQSYN
- 使用Verilog语言编写的使用SPI总线设置频率LM2346,可通过设置其R寄存器对其输出频率进行设置(需相应的射频电路相配合)。-The use of Verilog language use SPI bus frequency settings LM2346, can be by setting up its R register set of its output frequency (to be matched by corresponding RF circuitry).
top377
- 3955步进电机的驱动的cpld的verilog程序,经过测试,可以在ISPLEVER下调试,包括总线的译码等.非常完整-3955 stepper motor-driven Verilog CPLD' s procedures, after testing, can ISPLEVER debugging, including the bus, such as decoding. Very complete
time_display
- 用Verilog实现的电子时钟显示器,可以显示24小时制的时间-Using Verilog implementation of the electronic clock display, can display 24-hour time
divid5_VERILOG
- VERILOG实现无分频时钟,包括测试文件,经过验证可用-VERILOG is no difference between the frequency of the clock implementation, including test papers, can be used after authentication
11_FIR
- 11阶滤波器的verilog编程语言,可很好的实现滤波功能。-11-order filter verilog programming language, can achieve very good filtering.
XHDL3Version3·2·37
- vhdl语言和verilog语言转换工具 能很容易的实现两种语言的相互转换-verilog language vhdl language and conversion tools can easily achieve the conversion between two languages
uartverilog
- 实现cpld和pc机之间的串口通信,PC机传送到CPLD的信息,CPLD传回到PC机-Via verilog language ,cpld can communcate with pc.
VGA
- cpld实现vga驱动的程序,用verilog语言实现。-Via verilog language,it can complete the drive of vga module.
wddc_module
- 数字下变频的Verilog程序,测试可以直接使用,将A/D信号下变频为基带I,Q两路信号-Digital down conversion of the Verilog program, testing can be used directly to A/D signal down-conversion to baseband I, Q signals two
135VerilogExamples
- 网上找的verilog的例子,希望能对大家有所帮助~-Verilog Internet looking for examples, I hope you can help ~
uart_verilog
- 串口的Verilog源程序,可以用modelsim下进行仿真调试-Serial port of the Verilog source code can be carried out under the modelsim simulation debugging
Linux_bc
- 对vga接口做了详细的介绍,并且有一 ·三段式Verilog的IDE程序,但只有DMA ·电子密码锁,基于fpga实现,密码正 ·IIR、FIR、FFT各模块程序设计例程, ·基于逻辑工具的以太网开发,基于逻 ·自己写的一个测温元件(ds18b20)的 ·光纤通信中的SDH数据帧解析及提取的 ·VHDL Programming by Example(McGr ·这是CAN总线控制器的IP核,源码是由 ·FPGA设计的SDRAM控制器,有仿真代码 ·xili
1602
- 用verilog写的1602驱动 仿真已经通过,可以使用-Written in 1602 by verilog-driven simulation has been passed, you can use
AppendixC_quartus
- Quartus appendix - Can be useful if you start using quartus II to code in verilog-Quartus appendix- Can be useful if you start using quartus II to code in verilog
sourcefile
- 在Altera公司的Cyclone系列FPGA开发板上试验的按键中断程序,希望对那些学习中断开发的初学者有帮助。 pio_key.v是verilog编写的按键中断程序,对应四个按键,按其中任何一个键都可以发送一个中断; keyint.c是Nios中编写的C程序,用于检测按键的中断,如果检测到中断,会检测是哪个按键按下,从而执行相应的程序! -In Altera' s Cyclone series FPGA development board interrupt key test
count__10
- 这是VERILOG语言编写的程序,可在FPGA板上运行.有很大的作用.谢谢.-This is a program written in VERILOG language can be run in the FPGA board. Have a significant role. Thank you.
istarVHDL
- 压缩包包含有100个VHDL的程序实例,从简单到复杂有一个渐变的过程,非常适合自学CPLD/FPGA者(使用Verilog HDL者可以不下载)-Compression bags containing 100 examples of VHDL procedures, from the simple to the complex there is a gradual process, and is ideal for learning CPLD/FPGA are (using Verilog HD