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uart_nbit
- 用verilog语言写的串口通信程序,包括收发两个模块,可用于FPGA的通信中,可通过程序设置收发的位数,有很好的扩展性.-Verilog language used to write serial communication program, including the sending and receiving two modules can be used for FPGA communications, you can send and receive through the progr
digi_clock
- VerilogHDL程序，功能是可以实现一个数字电子时钟。-It s a Verilog-HDL procedure which can makes a digital electronic clock.
Altera_Verilog_Coding_Style_Proposal_final
- Altera的Verilog 代码规范，讲解的还可以-Altera' s Verilog code specifications, explanations can also be
RISCCPU
- 简单的CPU设计流程PPT，用于教学目的，可综合的verilog HDL设计。-A simple CPU design process PPT, for teaching purposes, can be integrated verilog HDL design.
LCD1602_Driver
- 自己课设上写的基于Verilog的LCD1602驱动器，能自定义字符，16x2显示位均已引出，可以用于纯硬件的电子钟等显示-To write their own lessons based on the LCD1602-based Verilog driver can customize the character, 16x2 display spaces have led to, can be used for pure hardware such as an electronic clock
an294_16x16
- Verilog编写的16x16的可交叉的CPLD程序,可用在16个VGA入,16个VGA输出-16x16 cross switch CPLD software wrote by verilog which can be used in 16 VGA input , 16 VGA output application
ntc
- NTC电阻在VERILOG HDL中的曲线表，使用1MA恒流源供电，用AD对其采集电压，并以12BIT形式输出查表即可达到实际温度值，本表占用450个12位存储单元-NTC resistor VERILOG HDL in the curve of the table, use the 1MA current source power supply voltages were collected with AD and in the form of the output look-up table
method
- i need to refer and search for calculator verilog.hope i can find answer from it.
PS2andRS232
- 基于Verilog语言PS2接口和RS232接口的实现 有文档说明,工程实例.可用来学习Verilog语言.-Based on Verilog Language PS2 interface and RS232 interface implementation are documented, project examples. Can be used to learn the Verilog language.
AUTO_START
- verilog 编写的代码 方便使用 能自启动的七进制计数器-verilog code written in easy to use can be self-starting of the seven binary counter
DDSVerilog
- Verilog 实现的DDS源码，可以配合NiosII软核使用 -Verilog realization of DDS source, you can use with soft-core NiosII
Verilogalotofexamples
- 关于VERilog 很多的例程，虽然不能处理比较大的应用，但是对于中小型的应用还是不错的-About VERilog lot of routines, although it can not handle larger applications, but applications for small and medium or good
digital_frequency
- 用verilog实现数字频率计的设计，具有自动换挡功能，采用t法和m法设计，低频显示周期。量程为0.5~10Mhz。开发环境为quartus-This is a method of designing a digital frequency-measuring device. It can measure frequency ranging from 0.5Hz to 10MHz. It is developed in the program of Quartus.
multi_cpu
- 使用Verilog语言编写的多周期CPU,能实现CPU24条指令，-Using the Verilog language multi-cycle CPU, can achieve CPU24 instructions,
trafficlights
- 基于verilog的交通灯实现，红绿灯交替转换，在规定的时间内，可以人为控制！-Verilog implementation based on the traffic lights, traffic lights turn conversion, within a specified time, you can artificially control!
veriloghdl
- Verilog HDL是一种硬件描述语言，用于从算法级、门级到开关级的多种抽象设计层次的 数字系统建模。被建模的数字系统对象的复杂性可以介于简单的门和完整的电子数字系统之间。数字系统能够按层次描述，并可在相同描述中显式地进行时序建模。-Verilog HDL is a hardware descr iption language, used from the algorithm level, gate-level to switch level design of a variety of
clk_div
- 分频计数器verilog源代码,包括实验说明文档,清晰易懂.-this code can easily be understood and teaches you how to divide the clock.
Average
- 利用ISE软件编写的求平均数的verilog程序，可以用来求平均数，用来对信号幅度的平均值进行计算-ISE software written request using the average of the verilog program can be used to seek the average used to calculate the average amplitude of the signal
sdram
- 用verilog语言编程实现的SDRAM模块，可用于配置在FPGA中-Verilog language programming with the SDRAM module, can be used to configure the FPGA,
DATA
- ８位输出端口模块，可用于配置在FPGA中，verilog语言编程实现-8-bit output port modules can be used to configure the FPGA in, verilog language programming