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stopwatch
- 这个程序是用verilog语言编写的秒表的小程序,可以精确到秒,有具体的程序,在开发板上实验成功!-This program is written in verilog stopwatch with a small program that can accurately to the second, there are specific procedures, the development board experiment is successful!
caideng
- 这个程序是用verilog语言编写的彩灯的小程序,使用状态机来实现,可以实现多种花型,有具体的程序!-This program is written in verilog small lantern, the use of state machine, you can achieve a variety of flowers, there are specific procedures!
Timer
- 嵌入式系统的单片集成定时器的Verilog实现。可实现多种配置模式,可作为通用的定时器设计模板-This is a standed timer for an SOC design.It can realize multible function need to design an micro process circut
MIT[1].Press_.Circuit.Design.with.VHDL._2004_.TLF
- This verilog vending machine code. We can eat beverage and soda with only $1.25-This is verilog vending machine code. We can eat beverage and soda with only $1.25
server
- This verilog vending machine code. We can eat beverage and soda with only $1.25-This is verilog vending machine code. We can eat beverage and soda with only $1.25
vending
- This is verilog vending machine code. We can eat beverage and soda with only $1.25 This decribes all schematic and state diagram. Ducksooyo~
can_tb
- verilog codefor can controller
verilog_frenqucy_div
- 使用verilog语言实现任意分频的设计,各位verilog学习者或者IC设计验证人员可以参考。-Verilog language use the design of any frequency, you verilog learners or who can refer to IC design verification.
vga
- vga显示,可以用fpgavga连接显示器显示彩条,简单实用的verilog程序-vga display, you can connect with fpgavga display color bars, simple and practical procedure verilog
lock-and-lcd
- 基于博创实验箱UP-CUP-FPGA2C35-Ⅱ和Verilog HDL硬件描述语言,分为按键输入模块、LED指示灯模块及LCD显示模块,采用按键BTN1、BTN2作为输入端输入四位密码与事先设定的密码进行匹配,由D1、D2、D3、D4四盏LED灯来指示输入密码的位数。开机时,LCD显示“HELLO! WELCOME!Enter the code:当”,密码输入正确时,LED灯D7亮,同时在实验箱LCD显示屏上显示字符串“Good! Well done!you are right!!!”,当密码
spi
- 用verilog实现的 SPI 源码,可以直接通过Quartus运行-SPI with verilog source implementation can be run directly through the Quartus ~ ~
netlist
- 可以实现4位延时。他是由matlab SG生成的verilog代码。-this program can realize delayed by 4bite.
jkdff
- 本工程为jk触发器的verilog语言程序工程,安全有效,可独立使用,可作为一个独立的模块。-This project is jk flip-flop verilog language program works, is safe and effective, can be used independently as a separate module.
lights
- verilog实现交通控制灯,能显示十字路口各方向状态,能红黄绿灯倒计时,能总体清零-verilog to achieve traffic control lights, can show the direction of crossing the state, the countdown to red, yellow, green and can generally be cleared
modelsim_guide_cn
- 使用ModelSim进行设计仿真ModelSim为HDL仿真工具,我们可以利用该软件来实现对所设计的VHDL或Verilog程序进行仿真,支持IEEE常见的各种硬件描述语言标准。可以进行两种语言的混合仿真,但推荐大家只对一种语言仿真。ModelSim常见的版本分为ModelSim XE和ModelSim SE两种,ModelSim版本更新很快-Design simulation using ModelSim HDL simulator ModelSim is, we can use the so
in-ModelSim-and-Xilinx-lib
- 在ModelSim SE中配置Xilinx的库函数 在Modelsim的安装根目录下新建一个文件夹,用来放xilinx的各个库文件,故可以起名 xilinx_lib。类似于Xinlinx的安装文件:\..\\Xilinx\verilog\src中的各个库文件,在xilinx_lib文件 下新建各个文件夹,命名规则为:若src中的文件夹名为unisims,则在xilinx_lib文件夹下新建 为unisims_ver的文件夹,与此雷同,新建名为simprims_ver、Xilinx
pskdem_fixed
- psk解调的定点仿真模型。另外DEC2HEX.C负责将十进制的数据文件转换为十六进制的数据文件,因为MATLAB输出数据格式为十进制,而NC-VERILOG能够读取的数据格式为十六进制,所以需要转换。-psk demodulation of the fixed-point simulation models. In addition DEC2HEX.C responsible for the data file is converted to decimal hex data file, as
rt
- 用Verilog编写的串口收发程序,通过参数调整,就可以设定/更改波特率,收发数据长度,已调试。-Serial transceivers with Verilog program, prepared by adjusting parameters, you can set/change the baud rate, send and receive data length, is debugging.
clock
- 用verilog语言编写的一个电子钟。能够显示时分秒,具有清零,设置时间的功能。-Verilog language with an electronic clock. Can display minutes and seconds, with a clear, set the time function.
VGA
- 改源码是采用VERILOG编写的驱动VGA显示屏的,能显示彩条和方格,是FPGA学习的好资料-Change the VERILOG source code is written using VGA display driver, and can display color bars and squares, is good information to learn FPGA