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  1. CORDIC_ip

    1下载:
  2. cordic IP core Features Each file is stand-alone and represents a specific configuration. The 4 parameters are: Rotation or Vector Mode Vector Precision Angle Precision Number of Cordic Stages All designs are pipelined
  3. 所属分类:ActiveX/DCOM

    • 发布日期:2008-10-13
    • 文件大小:447.46kb
    • 提供者:abcoabco
  1. cordic

    0下载:
  2. vhdl语言编写的cordic算法,实现了cordic的流水线运算。-cordic language vhdl algorithm cordic the pipeline operator.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-29
    • 文件大小:813byte
    • 提供者:lmy
  1. Cordic123

    0下载:
  2. for the pipeline cordic algorithm .it uses the vhdl language and good code and defines the algoritm correctly-for the pipeline cordic algorithm .it uses the vhdl language and good code and defines the algoritm correctly
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-02
    • 文件大小:106.68kb
    • 提供者:jai
  1. cordic_new

    0下载:
  2. Cordic with very high resolution. This program is developped by me. the maximal error is 0.04. You can use it for angle calculation.-Cordic with very high resolution. This program is developped by me. the maximal error is 0.04. You can use it for
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-01
    • 文件大小:1.32kb
    • 提供者:包一明
  1. cordic_mpy_100722

    0下载:
  2. 6bit & 32 bit pipeline CORDIC 乘法器-6bit & 32 bit pipeline CORDIC Multiplier
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-01
    • 文件大小:91.08kb
    • 提供者:彭洪
  1. cordic-verilog

    0下载:
  2. 用Verilog写的cordic相位鉴别,采用8级的流水线的硬件设计-Written using Verilog cordic phase identification, using 8-level hardware design of the pipeline
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-31
    • 文件大小:1.12kb
    • 提供者:朱子翰
  1. cordic

    0下载:
  2. 用verilog实现的一个基于流水线结构的正余弦信号发生器,六级流水线-Verilog realize a pipeline structure of the sine and cosine signal generator , six pipeline
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-02
    • 文件大小:1.34kb
    • 提供者:郭良谦
  1. cordic_atan

    0下载:
  2. 实现cordic vector模式 3级流水线 24级迭代-24 iterations of the three pipeline cordic vector mode
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-12-06
    • 文件大小:2.83kb
    • 提供者:呵呵呵
  1. cordic

    0下载:
  2. verilog实现的cordic算法,经典的流水线实现的cordic平方根的算法-cordic algorithm verilog implementation of the the classic pipeline implemented cordic square root algorithm
  3. 所属分类:Windows Develop

    • 发布日期:2017-11-10
    • 文件大小:797byte
    • 提供者:刘大远
  1. Cordic-arithmetic-pipeline

    0下载:
  2. FPGA实现基于Cordic算法的流水线结构设计,相关verilog语言代码-FPGA to realize the Cordic code
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-29
    • 文件大小:224.06kb
    • 提供者:孙永林
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