在maxplus上实现了一个5级流水线的mips cpu，含cache-In maxplus to achieve a 5-stage pipeline of the mips cpu, with cache

简单5级流水线CPU的verilog逻辑设计-Simple line 5 of the CPU logic design verilog

5级流水无cache,CPU实验，是学习VHDL的好资料，对于了解CPU很有帮助！-5-stage pipeline without cache, CPU test, is learning VHDL good information, very helpful for understanding the CPU!