搜索资源列表
DE2_LCM_Ball
- Altera的DE2測試LCM用，不再只是初始設定，會有方塊圖型碰壁反彈的運動。-LCM with Altera' s DE2 test, not just the initial set into a wall will block diagram-based campaign rally.
sy06
- LCD LED 显示时间代码 DE2嵌入式开发与应用-LCD LED Display Time Code
4945579081DCT_2D
- dct-20 verilog vhdl de2
VerilogCode_7_segment_decoder
- Verilog Code for seven segment decoder for the code to be implemented on Altera DE2 board
VerilogCode_8-bit_2to1_mux
- Verilog Code for 8 to 1 multiplexer for the code to be implemented on Altera DE2 board
VerilogCode_BCD_counter
- Verilog Code for a BCD counter and it is implemented on Altera DE2 board-Verilog Code for a BCD counter and it is implemented on Altera DE2 board
DE2_Web_Server
- 此文件是altera公司发布的基于DE2开发板的-web例程，能实现DE2开发板与计算机之间的信息传输，采用vhdL语言编写。-This file is Announces altera DE2 development board based on the-web routine, to achieve DE2 development board and the transfer of information between computers, using vhdL language.
SOCKET
- 基于de2开发板与pc机之间传输的实验，有详细的实验步骤和全面的资料，socket程序-De2-based development board and transfer between pc machine experiments, a detailed and comprehensive information on experimental procedures, socket program
sopc
- 基于sopc的视频终端的设计，提出了采用niosII软核在de2开发板上实现视频接收的功能-Based sopc video terminal design, the paper introduces niosII soft core in the de2 development board features for video receiver
hello
- VHDL语言，设计一个在DE2平台的8个七段数码管上循环显示HELL0的程序，采用按键控制循环的速度，慢速循环时间间隔为1S，快速循环时间间隔为200ms。-VHDL language, design a platform in the DE2 8 segment digital tube display HELL0 program cycle, the speed control loop using keys, slow cycle time interval for the 1S, fas
hmm
- 此代码是在DE2平台上实现汉明码的编码和译码，包括简易的通信信道。-hanming code encode decode
fpgaex5
- 测试反应时间，本例子是在DE2板上实现的测试人反应时间的程序-react time
USB20develop
- cy7c68013结合FPGA的开发笔记，本人原创，FPGA平台是DE2-cy7c68013+fpga develop note
CONTROL_DAC
- Seno Generator, for Altera DE2-70 This is a generator of seno signal and the output will be displayed in the VGA DAC of the board
Promediador
- This a Promediator for the Altera DE2-2 it use a looktable for obtein the data and then promediates the current sample with 3 past samples.-This is a Promediator for the Altera DE2-2 it use a looktable for obtein the data and then promediates the cur
DE2_LCM_CCD_sobel
- 基于DE2的图像边缘检测源代码，利用sobel实现其功能。-Image edge detection based on DE2 source code, using sobel to achieve its function.
DE2_SD_Card_Audio
- 这次演示展示了如何执行关于DE2开发- 70板，其中的音乐文件存储在SD卡和董事会可以播放的音乐文件通过其SD卡音乐播放器 CD质量的音频DAC电路。-This demonstration show how to implement an SD Card Music Player on the DE2-70 board, in which the music files are stored in an SD card and the board can play the music fil
tutorial
- another verilog VHDL tutorial, targeting altera DE2 board, but very intuituve.
DE2_Default
- Altera DE2 demonstration design, lot of interesting verilog code for synthesis
SRAM_1wait
- The aim of this vhdl file is to create a simple interface betwhen the sram and a basic processor on a semisync data bus. This was made using the test board DE2 from Altera.