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  1. getPDF

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  2. 本文分析的环境,利用内建自测试( BIST )和自动测试设备( ATE )和提出了封闭形式表达的故障覆盖率的函数数量的BIST的和ATE测试向量。-Analysis and Measurement of Fault Coverage in a Combined ATE and BIST Environment
  3. 所属分类:Editor

    • 发布日期:2017-03-31
    • 文件大小:505.81kb
    • 提供者:被遗忘
  1. fueifu

    2下载:
  2. 误删除、误格式化、误克隆、分区表丢失、误分区、PQ分区出错、病毒破坏等..OUTLOOK、OUTLOOK EXPRESS、FOXMAIL、LOTUS NOTES等邮件系统Word、Excel、PPT等OFFICE文档修复及各种文件无法正常使用.. office办公文档损坏或乱码,文档闪存CF卡/智能媒体SM卡/MS记忆棒/MMC多媒体卡/SD卡/XD卡/U盘/MP3/MP4,故障类型有:U盘/存储卡等无法识别,无法完成格式化,数据误格式化,误删除,覆盖等... 邮件误删
  3. 所属分类:Disk Tools

    • 发布日期:2017-05-11
    • 文件大小:2.84mb
    • 提供者:栾玉庆
  1. HCCR

    0下载:
  2. 运用仿生模式识别方法构建提取基本笔段的神经元序列覆盖手写体汉字图像, 分析笔段神经元间的拓扑性质, 将手写体汉字图像转化为具有容错表征方式的种汉字笔划类型组成的几何图形模仿人类汉字形码输人法统计具有冗余容错形状的笔划神经元类型、数量、位置、相合和相交点数量, 建立手写体汉字特征知识的数据结构表对一手写体汉字库中手写体汉字识别进行仿真实验。方法具有较强的“ 认知”手写体汉字的能力-Construction of the use of pattern recognition methods of e
  3. 所属分类:Graph Recognize

    • 发布日期:2017-05-04
    • 文件大小:1.18mb
    • 提供者:郭事业
  1. rage

    0下载:
  2. 逻辑内建自测试高故障覆盖率设计Logic BIST design of high fault coverage-Logic BIST design of high fault coverage
  3. 所属分类:Mathimatics-Numerical algorithms

    • 发布日期:2017-04-02
    • 文件大小:265.39kb
    • 提供者:vid2008
  1. Bist_codings

    0下载:
  2. In this paper, we have explained the purpose of FPGA testing. A built-in-self-test (BIST) is one type of testing. This test is performed internally to find any faults within a FPGA chip. This paper explains why testing is important to FPGAs. It also
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-07
    • 文件大小:14.28kb
    • 提供者:saravanan
  1. bist(1)

    0下载:
  2. In this paper, we have explained the purpose of FPGA testing. A built-in-self-test (BIST) is one type of testing. This test is performed internally to find any faults within a FPGA chip. This paper explains why testing is important to FPGAs. It also
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-01
    • 文件大小:3.07kb
    • 提供者:saravanan
  1. A-compact-AES-core-with-on-line-error-detection-f

    0下载:
  2. This paper presents a compact, low-cost, on-line error-detection architecture for a 32-bit hardware implementation of the AES. The implemented AES is specially designed for FPGA-based embedded applications, since it is tuned to specific FPGA logi
  3. 所属分类:Other systems

    • 发布日期:2017-05-03
    • 文件大小:918.04kb
    • 提供者:ANU MOHAN
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