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vga.niosII.compent.v
- 在cyloneIIFPGA平台下设计完成测试通过的VGA控制器代码。显存留在系统的SDRAM中，用FIFO作为缓冲。-in cyloneIIFPGA platform design is completed tests through the VGA controller code. RAM in the system SDRAM, and use as a FIFO buffer.
os8_2_fifo_ST_Blinky
- ucos_ii在str710f2z6上的移植及串口驱动（包含了fifo）源代码。其中“读我。txt”文件中有移植时做的简单笔记。希望对需要的初学者有所帮助。-ucos_ii str710f2z6 in the transplant and Serial Driver (including the fifo) source code. Which "I read. Txt "file a transplant when so simple notebook. Hope to b
syn_fifo
- 同步FIFO的verilog编码 -synchronous FIFO verilog coding synchronous FIFO verilog Synchronous Code FI FOR the verilog coding synchronous FIFO verilog coding
ram
- 本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ens
mp3blaster-3.1.3.tar.tar
- After the single transaction waveforms are implemented in the GPIF Designer, the next step is to integrate the USB portion of the overlying firmware with the GPIF Designer output to perform write and read operations to and from the external FIFO. T
FlashProgramTool
- After the single transaction waveforms are implemented in the GPIF Designer, the next step is to integrate the USB portion of the overlying firmware with the GPIF Designer output to perform write and read operations to and from the external FIFO. T
mp3
- The first task at hand is to set up the endpoints appropriately for this example. The following code switches the CPU clock speed to 48 MHz (since at power-on default it is 12 MHz), and sets up EP2 as a Bulk OUT endpoint, 4x buffered of size 512, a
pagec++
- 页面置换算法代码，语言采用c++。实现了FIFO算法，LRU算法，其中，LRU采用经典的LRU算法，由于该算法占用资源较大，多数OS采用改进的LRU算法.-pages replacement algorithm code language used c. To achieve the FIFO algorithm, the LRU algorithm, which, the LRU is a classical LRU algorithm, the algorithm occupy larger
INTSIO2
- 应用于51芯片的很经典的串口通讯程序源代码 （采用fifo方式）-chips used in 51 of the classic serial communication program source code (using fifo mode)
VHDL-ram_fifo
- VHDL的ram和fifo model code 包含众多的厂家
FIFO_LIFO_CRC
- 1：FIFO和LIFO程序；2：CRC校验码算法-1: FIFO and LIFO procedure; 2: CRC verification code algorithm
qasw sgww q
- 先进先出优先算法可以解决一些常见问题并为其源程序-FIFO arithmetic,it can solve some common question.It have source code.
fifo_ex4
- 深入浅出玩转FPGA代码 实验四FIFO模块 基于EP1C3-Layman Fun FPGA code EP1C3 based experimental four FIFO modules
uartfifo
- 基于FPGA的串口发送源代码，通过FIFO能够发送一段字符串。-FPGA-based serial port source code, a string can be sent through the FIFO.
DW_ahb_dmac_sbiu
- designware提供的dmac slave接口硬件描述语言-designware provide the source code verification VIP FIFO
ad_da_ctr
- 基于FPGA的ad和da转换Verilog代码，FPGA采用ep2c5芯片，做成异步fifo，ad芯片采用TI的ths1230,da芯片采用TI的TLV5619，仿真结果基本正确。-FPGA-based ad and da conversion Verilog code, FPGA using ep2c5 chip, made ??of asynchronous fifo, ad-chip using TI s ths1230, da chip uses TI s TLV5619, simula
small_fifo
- 同步fifo设计，仿真已通过，用Verilog编写，代码短小，易懂-Synchronous fifo design, simulation has been adopted, written with Verilog, code short and easy to understand
software_fifo
- 一种软件FIFO的实现源代码，供学习参考-FIFO implementation of a software source code reference for the study
fifoi
- 基于Xilinx Vertex2的可综合的2048x10位的读写可控制FIFO模块源代码，深度可控-Based on the Xilinx Vertex2 can be integrated 2048x10-bit read and write can control the FIFO module source code, the depth of controllable
workplace
- 是关于页面替换算法的代码模拟，用了三种算法，先进先出，第二次机会，时钟算法-Is on the page replacement algorithm code simulation, using the three algorithms, FIFO, a second chance, the clock algorithm