搜索资源列表
AsynchronousFIFO
- this is a source code design fifo assynchronus
123
- 该文件是16*16位先入先出fifo的源代码-The document is 16* 16-bit FIFO fifo source code
EZW
- C语言编写的EZW编解码算法，其中编码扫描的方式为先入先出原则-C language EZW codec algorithm, which scans the code for the principle of FIFO
FIFO1
- 一个功能非常完整的操作系统先进先出程序，代码简单易懂。-A very complete operating system FIFO procedures, easy-to-read code.
vc783453772452
- C++代码写的有关页面置换算法的程序 实现OPT 算法 (最优置换算法) 、LRU 算法 (Least Recently) 、 FIFO 算法 (First IN First Out)的模拟-C++ code written on the page replacement algorithm OPT program algorithm (the optimal replacement algorithm), LRU algorithm (Least Recently), FIFO algorit
vcyemianzhihuan
- 页面置换算法代码，语言采用c++。实现了FIFO算法，LRU算法，其中，LRU采用经典的LRU算法，由于该算法占用资源较大，多数OS采用改进的LRU算法.-Page replacement algorithm code, the language used c++. The realization of the FIFO algorithm, LRU algorithm, which, LRU classical LRU algorithm, the algorithm is occupied
SYNC_FIFO
- its simple fifo.which is used to first in first out for vhdl source code
FIFO_IN_VERILOG
- 基于Verilog的fifo的实现源码和测试文件-Fifo-based realization of the Verilog source code and test file
sun
- FIFo Page Replacement Source Code
caiyang
- 种用FPGA 实现对高速A/ D 转换芯片的控制电路,系统以MAX125 为例,详细介绍了含有FIFO 存储器的A/ D 采样控制电路的设计方法,并给出了A/D 采样控制电路的V HDL 源程序和整个采样存储的顶层电路原理图.-Species with FPGA to achieve high-speed A/D conversion chip control circuit, the system as an example to MAX125 details FIFO memory cont
p_t_s_422
- 应用于422串行通信中并行数据转串行的代码，可以结合fifo使用-422 serial communication used in parallel data to serial code, can combine the use of fifo
yuyincaiji
- 语音采集与回放系统源代码：1.为了使读音数据存储的时间更长，速度更快，选用了256K*16Bit的SRAM；2.为了减少单片机的控制复杂度，使用了FPGA来控制SRAM的读写操作，节约了不少单片机的I/O资源；3.为了以后的高速数据存储，本设计中加入了fifo,其位宽及深度可在程序中自由设置，方便灵活。-Speech acquisition and playback system source code: 1. In order to make pronunciation longer data
simpleFIFO
- FIFO的VHDL程序,硬件描述语言源码-FIFO process of VHDL hardware descr iption language source code
ECE348_LAB2_group11
- To write assembly code to implement a circular First In First Out (FIFO) buffer in the data memory of PIC18F452 microcontroller, using the microcontroller’s direct addressing mode and indirect addressing mode. This code serves as an assembly pro
LAB4
- To write assembly code to implement a circular First In First Out (FIFO) buffer in the data memory of PIC18F452 microcontroller, using the microcontroller’s direct addressing mode and indirect addressing mode. To expand on the FIFO assignment and imp
XR16M2550
- XR16M2550是一款高性能，具有16字节收发FIFO的异步全双工UART芯片，具有两路完全独立的UART通道。本资料包含完整的测试代码（ADS 1.2环境），中文应用文档，电路原理图，PPT讲解稿等。-XR16M2550 is a high-performance, with 16-byte receive FIFO, asynchronous full-duplex UART chip, with two-way completely independent UART channels.
X28xx_sourcecode
- word文档内有九个例子源程序： 例1、初始化锁相环及外设时钟函数 例2、.cmd格式文件举例 例3、定时器中断应用举例 例4、利用事件管理器输出多种频率的正弦信号输出例程 例5、SPI和DAC TLV 5617接口例程 例6、CAN总线消息发送例程 例7、使用FIFO缓冲发送数据 例8、使用FIFO缓冲接收数据 例9、ADC应用举例 -this word document includes nine examples of source
SFIFO
- 可以实现任意位的同步FIFO的verilog实现-the verilog code of a common SFIFO
linuxCode
- It is code for linux program. There are alarm， execle， fork， fifo，write and so on for sample.
vhdlfifo1
- fifo - source code for first in first out(fifo) using VHDL