搜索资源列表
actel_FPGA_example_source
- actel中的FIFO的使用的示例代码,对于使用actel环境的初学者有一定的帮助。-actel the use of FIFO in the sample code for beginners to use actel environment will certainly help.
AsynFIFO
- Verilog 代码 异步FIFO,可综合,综合效率高,cumming的经典方法。-Verilog code for asynchronous FIFO, Cumming s the classic method.
aFifo
- it is a vhdl source code for FIFO
SPI
- 含有fifo缓冲器的SPI接口源代码,用verilog语言实现-SPI Interface fifo buffer containing the source code, using verilog language
M2SDRAM_MR
- gray code based FIFO
wt97_fromLYS
- 关于小波变换的fifo作用下VHCL硬件语言代码-Fifo on wavelet transform under the action of the hardware language code VHCL
SlaveFIFO
- usb大全,第十八章实现slave FIFO数据传输的上位机程序源代码-usb Daquan, Chapter XVIII achieve slave FIFO data transfer PC source code
FIFOGJ
- USB大全第十八章实现slave FIFO数据传输的固件程序源代码-Chapter XVIII Daquan USB slave FIFO data transfer to achieve the firmware source code
fifo_synchrone.tar
- Systemc code of a FIFO (asynchrounous read , synchronous write)
61i_async_fifo_v5_1_vhdl
- VHDL Code for FIFO+coregen v5.0
USB_FPGA
- 基于Cyclone EP3C25的USB与CY60183传递数据的FIFO Verilog HDL源代码(FPGA端程序)-The program is a communication source code about USBCyclone EP3C25 transfering data via FIFO with CY60183 (only FPGA source code(verilog HDL) is included)
vhdl-ad9910
- ad9910 DDS板 VHDL源代码,在Cyclone II FPGA上调试通过,主要文件说明: Filename Function ----------------------------------------------------- dds_controller.vhd top entity, opcode decoding ddslib.vhd configuration,opcode definition dds_serial.vhd parallel to s
Verilog_HDL
- 基于Verilog_HDL的异步FIFO设计与实现,详细的步骤接收以及相应的代码,非常实用-Based on Verilog_HDL asynchronous FIFO design and implementation, as well as detailed steps to receive the corresponding code, very useful
qingqiufenye
- 设计一个请求页式存储管理方案,为简单起见。页面淘汰算法采用 FIFO页面淘汰算法,并且在淘汰一页时,只将该页在页表中修改状态位。而不再判断它是否被改写过,也不将它写回到辅存。-The professional English test source code
EDA-experiments-based-on-VHDL
- 上传的文件包括E有关EDA实验的程序,比如FIFO,秒表,数字钟,七段数码管,状态机检测序列-The files uploaded contain some source code of EDA experiments based on VHDL, such as FIFO, digital clock, stop watch, digital tubes and sequential detector.
run
- 自己动手写操作系统,小练习包括fifo.c\fork.c\popen.c等,保护模式,超过1M内存管理模式,等代码,生成的中间文件等,适合初学者参考!-Do-it-yourself write operation system, small exercises include fifo. C \ fork. C \ popen. C, and other protection mode, more than 1 M memory management mode, and the code, ge
uart
- 关于串口发送的verilog代码,实验中经常用到,已经用FIFO-it is about the uart transmit verilog code,very useful in experiment.
System_Demons
- 0.最简单的SystemC程序:hello, world. 1.用SystemC实现D触发器的例子,同时也演示了如何生成VCD波形文件。 2.用SystemC实现同步FIFO的例子。这个FIFO是从同文件夹的fifo.v(verilog代码)翻译过来的。 3.如何在SystemC中实现延时(类似verilog中的#time)的例子。 4.SystemC文档《User Guide》中的例子。注意和文挡中稍有不同的是修改了packet.h文件,重载了=和<<操作符。这其实
asdhbja
- 异步FIFO源代码 vhdl基于FPGA的设计,绝对值得一下,非常不给力的20 个字-vhdl code of asynchronous FIFo
ezwsrc-daima
- C实现EZW编辑器实例代码 C实现EZW编辑器实例代码,该源代码包含有6个文件: EZW.H - EZW编码器头文件 EZW.C - EZW编码器文件 MATRIX2D.H MATRIX2D.C - 编码器数据结果定义和数据操作 FIFO.H FIFO.C - 扫描方式定义:先入先出原则 LIST.H LIST.C - 零树结构定义和操作 UNEZW.C - EZW解码器 -C the EZW editor instance code C to EZW edi