搜索资源列表
asy_fifo
- 异步FIFO的实现方法，配源程序和WORD说明-Asynchronous FIFO implementations with source code and WORD Descr iption
trans_and_delete
- 1/2,3/4可配置的卷积码编码，其中需要用要FIFO的IP核-1/2, 3/4 convolutional code encoder can be configured with a FIFO wherein IP core
camera_fifo_ctrl
- camera异步接口中FIFO控制部分的源代码-FIFO control section of the source code in the asynchronous interface, camera
vhdl-Language-routine-highlights
- 工程中常用的VHDL控制模块，包括三态门，SDRAM，FIFO，PLL，RAM，FIlter等模块，非常实用的工程代码-Control module of VHDL is commonly used in engineering, including the tri-state gate, SDRAM, FIFO, PLL, RAM, FIlter module, very practical engineering code
asyn_fifo_bk
- 该verilog代码位手动编写的异步fifo。-This code is manually generated asychronous fifo.
matlab
- 单服务台模型，一分析fifo排队规则的分析模型，此代码可以计算出分析数据，而且可以绘出二维分析图-Single-desk model, an analysis of the FIFO queuing discipline analysis model, this code can calculate the analysis of data, and you can draw two-dimensional analysis chart
prj_5
- FIFO Using MyFIFO_Block_Memory_v7_1 with verilog code
AN65974---FPGA-FX3-firmware
- FPGA与USB3.0芯片CYUSB3014的接口程序，作为slave fifo的固件代码-Source files for FPGA code and FX3 firmware
sync-and-asyn_FIFO_verilog
- 同步与异步FIFO的verilog实现，包括源代码，testbench，测试以及综合通过，还有相关参考资料-Synchronous and asynchronous FIFO verilog achieve, including source code, testbench, test and integrated through, as well as related references
EZW-sourcecode
- EZW举例 该源代码包含有6个文件： EZW.H － EZW编码器头文件 EZW.C － EZW编码器文件 MATRIX2D.H MATRIX2D.C － 编码器数据结果定义和数据操作 FIFO.H FIFO.C － 扫描方式定义：先入先出原则 LIST.H LIST.C － 零树结构定义和操作 UNEZW.C － EZW解码器 -EZW Example The source code contains six files: EZW.H- EZW encod
61EDA_C2212
- 红色飓风II开发板USB2FPGA USB驱动程序，由verilog编写，包括源码和FIFO测试程序-Red Hurricane II development board USB2FPGA USB driver from verilog preparation, including source code and test procedures FIFO
UART_FIFO
- Verilog编写的串口配合FIFO的代码，对大家学习串口和FIFO有一定帮助-Verilog prepared with FIFO serial code, we learn the serial port and FIFO have some help
syn_fifo
- 同步FIFO源代码，使用Verilog编写，用户可以轻松转换成VHDL。-Synchronized FIFO source code
AN66806
- 提供了利用 GPIF 对 FX2LP 与同步 FIFO CY7C4625-15AC 之间的接口进行设计的源代码-Provides for the use of GPIF FX2LP and synchronization FIFO CY7C4625-15AC to design the interface between the source code
LATTICE_ASYNFIFO
- LATTICE FPGA FIFO 程序例程，工程详细，全部源代码上传 -LATTICE FPGA FIFO routine, detailed engineering, all source code uploaded
VGA800
- 本代码用verilog语言，配合quartus里自带的fifo来简单实现vga显示屏的操作，重点在于弄清楚时序。代码中被注释的部分也可以用于彩色条纹的测试。-The code to use verilog language, with quartus in fifo comes to simply achieve vga screen operation, with emphasis on clear timing. The code portion of the notes can be te
fifo_read
- 此代码实现linux进程间通讯代码，这个是进行FIFO读操作的c语言代码。-This code implements linux inter-process communication code, this is a FIFO read operation for the c language code.
fifo_write
- 此代码实现linux进程间通讯代码，这个是进行FIFO写操作的c语言代码。-This code implements linux inter-process communication code, this is a FIFO write operation for the c language code.
SDRAM_LCM_PROJECT
- sdram源代码，输入16数据位数据到sdram，再传送到fifo，通过uart端口发送出去。-sdram source code, data input 16-bit data to sdram, then transmitted to the fifo, sent through uart port.
async_pulse
- asynchronous fifo with pulse input write by verilog code