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FIRvhdl
- 用vhdl实现一个fir滤波器 设计要求： 1．最小阻带衰减-30db。 2．带内波动小于1db． 3．用MATLIB与MAXPLUS2联合设计与仿真-use VHDL to achieve a fir filter design requirements : 1. The smallest stop band attenuation - 30dB. 2. With fluctuating within less than 1DB. 3. With MATLIB with MAX
34105908-Multipliers-Using-Vhdl
- ABSTRACT: Low power consumption and smaller area are some of the most important criteria for the fabrication of DSP systems and high performance systems. Optimizing the speed and area of the multiplier is a major design issue. However, area and
FIR
- 采用vhdl语言 设计FIR滤波器，经调试好使，献给广大硬件开发的朋友参考学习-FIR filter design using vhdl language, so that upon commissioning, the development of friends dedicated to the general hardware reference learning
FIR-LOOP-
- 数字接收机中的FIR滤波器，环形滤波器设计参考,VHDL代码-the FIR filter， loop filter design in a digital receiver,vhdl code
fir-filter
- fft的vhdl实现源代码，具体的有心情有兴趣的可以自己下载下来看下，因为我也是在入门中不懂。-fft verilog HDL
26352153-VHDL-Coding-for-FIR-Filter
- VHDL filter design powerpoint
FIR
- fir数字滤波器，VHDL语言编程，先通过MATLAB计算得到参数。-fir digital filter VHDL language programming, first obtained by MATLAB calculated parameters.
fir
- 利用VHDL和Verilog HDL语言实现FIR滤波器-Using VHDL and Verilog HDL language to realize FIR filter
fir
- 该程序实现了一个FIR滤波加速器，该程序在FPGA板上开发，通过使用VHDL语言来定义RS232端口的使用-design a FIR Filter Accelerator based on FPGA board and RS232 interface using VHDL language.
fir
- 本历程是用 VHDL实现fir滤波器cds算法的历程，熟悉CDSsuanfa -This process is to achieve fir filter algorithm cds course, familiar with CDSsuanfa
FIR-filter
- VHDL设计的FIR滤波器，由3个文件组成：FIR.VHD、PACK.VHD和signed.vhd。testfir.vhd为测试平台。-VHDL designed FIR filters, composed by the three documents: FIR.VHD, PACK.VHD and signed.vhd. The testfir.vhd is a testbench.
FIR
- 用VHDL语言写的FIR滤波器，简单易懂，拿来直接用，10节窗函数法带通滤波器-Write VHDL FIR filter, easy to understand, be used directly, 10 bandpass filter window function method
FIR
- 用VHDL写的FIR滤波器，前端有DDS产生波源-Write VHDL FIR filter, front end DDS generated wave source
Ref-exstfir-VHDL-Code
- code for an fir filter of n length order with different multipliers and adders
filter
- 此程序是一个用VHDL语言编写的fir滤波器。经过了仿真验证，很好用。-This procedure is a VHDL language fir filter. After the simulation, very good use.
FIR-VHDL
- 15阶FIR滤波器的设计VHDL代码 ，包括顶层模块及各模块的VHDL设计代码-15 order FIR filter design VHDL code, including the top-level module and each module VHDL design code
VHDL
- VHDL. FIR 滤波器 声音处理。 I2C configuration inerface, -VHDL. FIR filter sound processing. I2C configuration inerface,
fpga-fir
- 使用Quartus II 9.1完成低通FIR滤波器的实现，在任意开发板上都能实现。操作简单，使用的是VHDL和Verilog语言-Use the Quartus II 9.1 the realization of the complete low pass FIR filter, can be implemented in any development board. The operation is simple, the use of VHDL and the Verilog langua
FIR
- this file is vhdl code of fir filter
VHDL-FIR-filters
- ynthesizable FIR filters in VHDL with a focus on optimal mapping to Xilinx DSP slices. This repository contains a transposed direct form, systolic form for single-rate FIR filters and a custom parallel polyphase FIR decimating filter. The VHDL has be