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filter_lpm_shaping
- 4倍内插值的fir成型滤波器,语言vhdl,工程已建立,可以直接运行-4x interpolation of fir shaping filter, language vhdl, project has been established, you can directly run
fir_test01
- 在quartus ii 环境下,用VHDL语言编写的基于ALTERA 的IP核的FIR低通滤波器。 -In quartus ii environment, using VHDL language ALTERA FIR IP core based on the low-pass filter.
ddc1
- 数字上变频,包括DDC,CIC,补偿FIR,FIR。-Digital down conversion VHDL procedures, FIR, CIC filter
Digital-signal-process-of-PFGA
- 数字信号处理 包括滤波器IIR FIR CORDIC的FPGA实现 资料中是VHDL语言 相应的配套包verilog程序-Digital signal processing includes a filter IIR FIR CORDIC on FPGA is VHDL language data corresponding supporting package verilog program
sin
- 用VHDL语言编写实现以下功能:用PLL,复位器,分频器,同步时钟,计数器来产生正弦波,再在其上加扰,用FIR滤波器进行滤波整形,最后得到输出。-Using VHDL language to achieve the following functions: PLL, reset, clock synchronization, frequency divider, counter to generate sine wave, and then scrambling on the filter sh
DSP
- FIR Digital Filter Design (DSP example) tested by Weijun Zhang, 04/2001 VHDL Data-Flow modeling KEYWORD: generate, array, range, constant and subtype- FIR Digital Filter Design (DSP example) tested by Weijun Zhang, 04/2001
xiaosong-fpga
- FIR数字滤波,亲自测试,都是源码,希望可以帮到大家,谢谢,谢谢!大家要好好学习呀,学习好VHDL(FIR digital filter, personally tested, are source code, and I hope to help you, thank you, thank you! We should study hard, good study, VHDL)