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用verilog编写的fir滤波器程序，开发环境可以用ise quartus或active hdl等-verilog prepared with the fir filter process development environment can be used ise quartus or other active hdl
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Verilog 编写的fir滤波器，可以实现fir滤波器的功能-Verilog prepared by the fir filter can achieve fir filter function
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个DDC使用的级联滤波器，结构CIC6+CFIR+PFIR,DDC using a cascade filter, the structure of CIC6+ CFIR+ PFIR
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高通滤波器的verilog实现，对初学者设计FIR有好处，分布式算法-Verilog implementation of high-pass filter, FIR design is good for beginners, distributed algorithm
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使用verilog 写的FIR滤波器，里面并有matlab程序，是从altera官网下来的。。希望对大家游泳。-Use verilog to write the FIR filter, which have matlab and procedures, are down from the official website of the altera. . Everyone would like to swim.
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基于DSPbuilder搭建的DDC，里面包括CIC滤波器，FIR低通滤波器，HB半带滤波器，NCO等，实现了GC5016芯片的功能-DSPbuilder erected based on DDC, which include the CIC filter, FIR low-pass filter, HB half-band filter, NCO, etc. to achieve the function of the GC5016 chip
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FIR抽取滤波器，抽取系数3，Verilog版本，数字下变频-FIR decimation filter, extraction coefficient of 3, Verilog version of the digital down-conversion
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用verilog语言编写的一个FIR滤波器的程序-Verilog language with a FIR filter process
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用Verilog写的fir滤波器，16阶8位位宽，看看吧-Written using Verilog fir filter, 16-order 8-bit wide, to see if it
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一种fir滤波器的verilog程序，非常实用-fir filter very good write by verilog
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数字低通FIR滤波器Verilog实现代码-Verilog digital FIR filter implementation code
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基于FPGA的自适应FIR滤波器的verilog设计与实现-Adaptive FIR Filter Based FPGA Design and Implementation of verilog
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verilog的32阶FIR低通滤波器描述-verilog 32-order FIR low-pass filter described
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RobustVerilog generic FIR filter
In order to create the Verilog design use the run.sh scr ipt in the run directory (notice that the run scr ipts calls the robust binary (RobustVerilog parser)).
The filter can be built according to 3 differe
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基于verilog的FIR滤波器程序设计（调试过的的）-verilog ，
-Verilog program of FIR filter design (debug)-Verilog,
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基于FPGA开发的11阶半带升余弦FIR滤波器，用在阅读器基带滤波时的抽取滤波器使用，采用verilog语言实现。-Raised cosine FIR filter based FPGA development 11 order of half-band decimation filter used in reader baseband filtering, using verilog language implementation.
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FIR 滤波器 verilog 语言编写 很实用-FIR filter design
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FIR滤波器的仿真，使用ISE软件verilog语言。其中滤波器系数为matlab产生的.coe文件，并产生testbench文件进行仿真。-FIR filter verilog coe testbench
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用verilog语言实现数字电路低通滤波器(Implementation of digital circuit low-pass filter using Verilog language)
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经典的verilog语言实现转置型FIR滤波器的代码(Code of Inverted FIR Filter Implemented by Classical Verilog Language)
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