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  1. TIMEFACEDETECTIONANDLIPFEATUREEXTRACTIONUSINGFPGA

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  2. Abstract—This paper proposes a new technique for face detection and lip feature extraction. A real-time field-programmable gate array (FPGA) implementation of the two proposed techniques is also presented. Face detection is based on a naive Bay
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2016-05-05
    • 文件大小:27.09mb
    • 提供者:ramanaidu
  1. edge-detection1

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  2. 基于FPGA开发环境,根据Sobel model算法,关于边缘检测的verilog代码。-the code of edge detection based on verilog.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-12-15
    • 文件大小:1kb
    • 提供者:Oscar
  1. soble

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  2. 基于FPGA的Sobel边缘检测算法的实现与仿真。此程序提供算法的verliog实现。(Implementation and Simulation of Sobel edge detection algorithm based on FPGA. This program provides the verliog implementation of the algorithm.)
  3. 所属分类:VHDL/FPGA/Verilog

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