搜索资源列表
Wave_ROM
- 基于RAm的FPGA实现DDS,有测试文件
mif
- 编制FPGA中RAM所需要的MIF文件 编制FPGA中RAM所需要的MIF文件
6713emiftofpgatopci
- 6713emiftofpgatopci,这个是完整的一套从6713的emif到fpga的双口ram,然后主机通过9054到双口ram,交换数据完成
ddr_reader
- xilinx fpga 的 micoblaze 下的 ddr ram 读程序
an_dcfifo_top_restored
- alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输 ,值得学习。
read_wirte_ram
- FPGA实现双口RAM功能,从而用FPGA实现双控制器间的数据交换-FPGA realization of dual-port RAM functions, the exchange of data between the dual-controller with FPGA
dual_RAM.rar
- actel fusion startkit FPGA开发板试验例程,可实现2k8的双口ram,实现数据存储,缓冲。包含verilog HDL 语言源码,actel fusion startkit FPGA development board test routines, can be realized 2k8' s dual-port ram, achieving data storage, buffer. Language source code contains the verilog
ram_fifo_ram
- 程序实现了在FPGA内部开辟RAM+FIFO+RAM的IP核进行数据之间的调试。方便需要用到的童鞋进行参考。已通过modelsim调试-Implemented within the FPGA program to open up RAM+ FIFO+ RAM for data between the IP core debugging. Need to use the shoes for easy reference. Has passed debug modelsim
synth_fft
- 甘地大学电子专业Ray Ranjan Varghese设计的FPGA实现FFT,采用的是单精度的浮点,采用IEEE745格式的浮点+ROM RAM的方式成功实现FFT,含有设计报告和设计源代码,并有测试文件,真的很不错。 -Gandhi University of Electronic Design Professional Ray Ranjan Varghese FPGA realization of FFT, using a single precision floating-point,
mem_ctrl_latest.tar
- 存储器控制FPGA程序,包括ram,fifo,sdram,flash等。-FPGA memory control processes, including ram, fifo, sdram, flash and so on.
DDR_FLASH_VHDL_Verilog
- FPGA DDR 外部RAM 读写的verilog代码,以及FLASH的vhdl代码-DDR SRAM READ AND WRITE VERILOG CODE ,FLASH VHDL CODE ,FPGA
irig
- irig-b 单片机 解析 MSP430系列单片机是集成度高、超低功耗的16位单片机。Cyclone系列芯片是Altera公司推出的低价格、RAM可达288 kb的高容量的FPGA。IRIG-B码广泛应用于靶场时间信息的传递和各系统的时间同步。详细介绍了IRIG-B码解码电路和调制电路的硬件设计。MSP430的软件采用C语言编写,使程序有很强的可移植性。-irig-b microcontroller MSP430 Microcontroller analysis are highly int
caiji1
- 利用两个双口ram做的乒乓操作,采集高速大容量数据,fpga写,arm读-Two dual-port ram to do the ping-pong operation, collecting high-speed large-capacity data, fpga write, arm reading
3ram_ram
- 程序实现了FPGA内部RAM之间的数据传输。采用了3片RAM+RAM的结构形式。已通过调试-Procedures to achieve the data transmission between the FPGA internal RAM. Uses 3 RAM+RAM structure. Has passed through debugging
lpm_ram
- 一个基于quartus的LPM_RAM例子,VHDL语言写的,通过仿真测试-Quartus the LPM_RAM based on examples, VHDL language, and through simulation testing
fifo_test
- FIFO读写verilog程序,经本人验证,能够顺利运行。实现FPGA对fifo的控制。-the example of writing and reading the fifo ram of the fpag,i have already tested it.
fifo_ram
- 同步fifo, 基于FPGA的VHDL编程,已调试。-fifo-ram
read
- 在FPGA内部实现RAM块中数据的读出,简单方便。-Internal implementation in FPGA block RAM read data
ramtest
- 用verilog语言往内部FPGA的sram中读写数据,即把1—4写入ram的1—4的地址里-Verilog language within the FPGA with the sram to read and write data, that is 1-4, 1-4 to write the address in ram