详细介绍LVDS，CML，PECL的电路原理，以及他们之间的耦合方式，通信专业人士用。-Details LVDS, CML, PECL circuit principle, as well as the coupling between them, communication with professionals.

• Dual ADC with 8-bit Resolution • 500 Msps Sampling Rate per Channel, 1 Gsps in interleaved Mode • Single or 1:2 Demultiplexed Output • LVDS Output Format (100Ω) • 500 mVpp Analog Input (Differential Only) • D

Dual ADC with 8-bit Resolution • 1 Gsps Sampling Rate per Channel, 2 Gsps in Interleaved Mode • Single or 1:2 Demultiplexed Output • LVDS Output Format (100Ω) • 500 mVpp Analog Input (Differential Only) • Differenti