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cpu-maxplus
- MaxplusII编写的简易cpu，可实现简单加减法等操作-MaxplusII summary prepared by the cpu can realize simple addition and subtraction, etc
mips
- 在maxplus上实现了一个5级流水线的mips cpu，含cache-In maxplus to achieve a 5-stage pipeline of the mips cpu, with cache
CPU
- 实现简单CPU功能的源码，可以实现加减乘除和移位功能，VHDL代码，程序运行在MAX PULS和Quartua上。-The purpose of this project is to design and simulate a parallel output controller (POC) which acts an interface between system bus and printer. The Altera’s Maxplus Ⅱ EDA tool is recommended
CPUsourcecode
- 本设计实现了一个具有标准的32位5级流水线架构的MIPS指令兼容CPU系统。具备常用的五十余条指令，解决了大部分数据相关，结构相关，乘除法的流水化处理等问题，并实现了可屏蔽的中断网络。-This design implements a standard 32-bit 5-stage pipeline architecture of MIPS instruction compatible CPU system. Instructions with more than 50 commonly use
zreda7
- 详细具体的cpu设计maxplus源代码（附图）能完成cpu的基本功能。-Cpu design maxplus detailed and specific source code (with photos) to complete the basic functions of cpu.