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vhdl实例-完整微处理器系统模型
- vhdl实例-完整微处理器（cpu）系统模型 -VHDL-integrity microprocessor (CPU) system model
NAND01GR3B_VH1
- nand flash NAND01GR3B (st)的仿真模型 （VHDL） 的-nand flash NAND01GR3B (st), the simulation model (VHDL)
VHDL-ram_fifo
- VHDL的ram和fifo model code 包含众多的厂家
Original-8051 Vhdl Model
- 這是Originl公司出的8051 VHDL source code.-It s a 8051 VHDL source code issued by Original.
sd_reader.rar
- SD卡读卡器模块的VHDL及软件驱动代码，可作为外设挂接在Avalon总线上。支持以SD模式、4线模式读取。在24MHz时钟驱动下读取速率可达8MByte/s,SD card reader module and software drivers VHDL code, can be articulated as a peripheral bus in Avalon. To support the SD model, 4-wire mode read. Driven by the 24MHz clo
flash_operator.rar
- 本代码为控制三星公司nand flash，型号k9f5608，实现了读写和擦除操作，方便调用,The code for the control of Samsung nand flash, model k9f5608, achieved a read-write and erase operations to facilitate the call
MT29FxxG08xx.rar
- MT的NAND FLASH MT29FxxG08xx系列的Verilog仿真模型，包含详细说明，试验证明，非常准确。,MT of the NAND FLASH MT29FxxG08xx series of Verilog simulation model, contains a detailed descr iption, testing proved very accurate.
EEPROM_RD_WR.rar
- 本程序包含：EEPROM的功能模型(eeprom.v)、读/写EEPROM的verilog HDL 行为模块（eeprom_wr.v）、信号产生模块（signal.v）和顶层模块(top.v) ，这样可以有一个完整的EEPROM的控制模块和测试文件，本文件通过测试。,This procedure includes: EEPROM of the functional model (eeprom.v), read/write EEPROM acts of verilog HDL modules (e
Omnivision SCCB interface verilog model
- Omnivision SCCB interface verilog model
SD_Host_Model_513_02
- 可做SD的simulation model-SD can do the simulation model
daout-Sine-wave
- 正弦波的vhdl输出，使用VHDL编写的，已经通过调试-Sine wave output of the VHDL, the use of VHDL prepared already through debugging
IS61WV51216
- iss simulation model for 512KX16 SRAM
uart-vhdl-testbench
- simple uart vhdl behavioural model (package) vhdl testbench example
aips7108.tar
- SATA 仿真模型 SATA 仿真模型-Simulation Model SATA SATA SATA simulation model simulation model
Simulink-to-VHDL-Route
- This paper presents the way of speeding up the route from the oretical design with Simulink/Matlab, via behavioral simulation in fixed-point arithmetic to the implementation on either FPGA or custom silicon. This has been achieved by porting
Verilog-Round-Robin-Arbiter-Model.tar
- Verilog Round Robin Arbiter Model
eeprom-model
- 基于fpga的eeprom设计，适合用于eeprom的仿真-eeprom model based on FPGA
serialdivider-model
- this is serial divider model vhdl file and testbench not included
Op-Amp-Model(VHDL-AMS)
- 模拟信号模型-运算放大器模型Op Amp Model的VHDL-AMS程序-Analog signal model- op amp model Amp Model VHDL-AMS Op program
Profibus DP - VHDL BUS Model
- Profibus DP VHDL总线模型设计,包含主站和从站VHDL设计代码和测试代码