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multiplexer
- 几种常用乘法器的Verilog、VHDL代码-Several common multiplier Verilog, VHDL code
Multiplexer
- 这是一个用vhdl硬件描述语言实现的乘法器而不是多路选择器-this is an implimentation of an multiplier rather than multiplexer.
mux_reg
- VHDL code for a multiplexer and a parallel/serial in parallel/serial out shift register
16-1MUX
- 16 down to 1 Multiplexer in Vhdl
multiplexersemultiplexer
- this project is based on 2*1 and 4*1 multiplexer and 1*2 and 1*4 demultiplexer using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be us
MuxDemux_E1_E3
- Multiplexer and demultiplexer from E1 to E3 stream
cpu
- 包括1) 时钟发生器 2) 指令寄存器 3) 累加器 4) RISC CPU算术逻辑运算单元 5) 数据控制器 6) 状态控制器 7) 程序计数器 8) 地址多路器 -1) clock generator 2) instruction register 3) accumulator 4) RISC CPU arithmetic logical unit 5) of the data controller 6) state controller 7),
Multiplexer
- Source code of multiplexer on VHDL. The compilation is done in Quartus II for Cyclone II.
MuxDemux_E1_E3
- E3 -Mux / Demux - Multiplexer of 16 E1 Channels-E3 -Mux / Demux - Multiplexer of 16 E1 Channels
active-hdl-vhdl-code
- this vhdl source code for multiplexer,half adder,full adder,counter etc. for using in ACTIVE HDL and other vlsi softwares.-this is vhdl source code for multiplexer,half adder,full adder,counter etc. for using in ACTIVE HDL and other vlsi softwares.
VHDL
- 时钟发生器用于生成不同的时钟信号clock、clk2、fetch与alu_clk，产生的时钟信号clk送往寄存器与状态控制器，时钟信号clk2送往数据控制器与状态控制器，信号fetch送往数据控制器与地址多路器，信号alu_clk送往算术逻辑单元。-Clock generator to generate different clock signals clock, clk2, fetch and alu_clk, generated clock signal sent to register w
vhdL
- VHDL多路选择器 （使用case语句）-VHDL multiplexer (using case statement)
vhdl
- 用VHDL语言实现的多路选择器，分别有if、case等不同的方法-VHDL language with the multiplexer, respectively, if, case and other different ways
83_multiplexer
- vhdl 语言 开发 程序比较详尽 微处理器 里面的部件-vhdl language development program inside the more detailed parts of the microprocessor
multiplexer
- multiplexer unit designed in vhdl VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware Descr iption Language.
mux
- ABOUT MULTIPLEXER VHDL CODE
The-VHDL-various-basic-code
- VHDL的各种基本代码 包括4选1,8选1多路选择器，8位全加器，加1减1计数器，序列检测器，异步清零16位加减可控计数器，数码管扫描程序，双2选1，状态机等基本程序！-VHDL basic code including 4 election 1,8 to 1 multiplexer selector, 8-bit full adder, plus 1 minus 1 counter sequence detector, asynchronous clear 16 plus or minus
VHDL
- 3-8译码器 4-2优先编码器 4选1多路选择器-3-8 4-2 priority encoder decoder 4-to-1 multiplexer
1.1Generic-Mux-VHDL
- generic 2to1多路复用器,用behavior和structure两种方式写的!-generic 2to1 multiplexer with behavior and structure are two ways to write!
decoder-and-multiplexer
- code vhdl decoder and multiplexer