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200628111717
- DFT(Discrete Fourier Transformation)是数字信号分析与处理如图形、语音及图像等领域的重要变换工具，直接计算DFT的计算量与变换区间长度N的平方成正比。当N较大时，因计算量太大，直接用DFT算法进行谱分析和信号的实时处理是不切实际的。快速傅立叶变换(Fast Fourier Transformation，简称FFT)使DFT运算效率提高1～2个数量级。其原因是当N较大时，对DFT进行了基4和基2分解运算。FFT算法除了必需的数据存储器ram和旋转因子rom外，仍
FFT
- 流水线模数转换电路输出信号做fft后求SNR,SNDR的matlab程序-matlab fft program for SNR and SNDR of pipelined analog to digital converter（ADC）
FPGAbasedontheworkofthe1024-pointpipelinedFFT
- 基于FPGA的1024点流水线工作方式的FFT实现,适合fpga的技术人员做信号处理参考-FPGA based on the work of the 1024-point pipelined FFT approach the realization of the technical staff for doing fpga signal processing reference
cfft
- The FFT architecture is pipelined on a rank basis each rank has its own butterfly and ranks are isolated from each other using memory interleavers.-The FFT architecture is pipelined on a rank basis each rank has its own butterfly and ranks
cf_fft_latest.tar
- 整个设计使用了流水线设计，运用了同步的使能和复位信号。这是一个4k点的fft。实部和虚部均为18bit，总共为36bit精度。-All designs are pipelined with a synchronous enable and reset. 18 bit precision, real and imaginary. Total is 36 bits.
pipelined_fft_256_latest
- FFT的ip核，是256位的，可以用在FPGA上进行FFT操作。-FFT' s ip core, is 256, and can be used in FPGA on FFT operation.
cf_fft_latest.tar
- The FFT architecture is pipelined on a rank basis each rank has its own butterfly and ranks are isolated from each other using memory interleavers. This FFT can perform calculations on continuous streaming data (one data set right after anot
pipelined_fft_64_latest.tar
- This containg pipelined FFT code for FPGA.
Pipelined-ADC
- pipelined ADC, 各种参数可调，最后包括fft分析和整个传输曲线-pipelined ADC, adjustable parameters, and finally including the entire transfer curve analysis and fft
pipelined_fft_256_latest[1].tar
- 256点的流水FFT，经本人使用完全满足要求。-256-point FFT of pipelined
non_continues_ifft
- 非流水线数据输入方式的FFT调核实现，功仿正确，由于采用基2的方式，输出需花很长的时间，因此，前面需要加载FIFO存取中间来的数据，保证FFT处理的时间。因此，对输入数据流的时钟频率不能太高！ -Non-pipelined FFT of input data transfer nuclear achieved successful imitation is correct, the way thanks to the base 2, the output need to spend a lo
FPGA-based-FFT-implementation
- 基于FPGA的FFT算法硬件实现 设计了一 种基于 FPGA 的 1 024点 16位 FFT算法, 采用了基 4蝶形算法和流水线处理方式, 提高了 系统 的处理速度, 改善了系统的性能 -FPGA-based FFT algorithm hardware design of a 1024 16-bit FPGA-based FFT algorithm using a radix-4 butterfly algorithm and pipelined approach to improv
8-point-pipeline-fft-by-verilog.pdf
- 简单的8位基2 流水 fft verilog-Simple 8 base 2 pipelined fft verilog
pipelined_fft_64_latest.tar
- pipelined fft 64 latest OK
SDF-DIF-FFT-pipelined
- vhdl code for pipelined single delay feedback radix 2 square FFT
pipelined_fft_256
- pipelined fft/ifft 256 point ip core
sdf_fft_8pt
- 8pt sdf fft pipelined
sdf_fft_64pt_tb
- 64 pt fft tb sdf pipelined
pipelined_fft_256_latest.tar
- 一个256流水线结构的FFT实现，用于FPGS实现，xilinix(A 256 pipelined structure of the FFT implementation, for FPGS implementation, xilinix)
pipelined_fft_64-master
- Pipelined FFT/IFFT 64 points (Fast Fourier Transform) IP Core User Manual