搜索资源列表
altera_lcd_controller
- quartus II-sopc builder avalon总线LCD控制IPCORE-quartus II-sopc builder avalon Bus LCD controller IP CORE
VHDL_Memory_Library_Code
- 通用存储器VHDL代码库,The Free IP Project VHDL Free-FIFO, Quartus standard library. -generic VHDL code for memory, The Free Project VHDL IP Free-FIFO, Quartus standard library.
CrackQII60
- quartus6.0+nios2 6.0的License,将hostid改为你自己的网卡号即可使用quartus和nios6.0的全部功能-quartus6.0 nios2 6.0 License, hostid to read your own card can be used quartus, and the full functionality of nios6.0
Crack_QII60_b178
- Quartus II 6.0完全Crack文件-Quartus II 6.0 document completely Crack
multi8x8
- 节约资源型 8位*8位 运算VHDL代码，采用串行运算，8 个时钟周期完成一次运算。QUARTUS下已验证-resource conservation-8 * 8 Operational VHDL code, using serial computation. 8 clock cycles to complete an operation. QUARTUS has been under test
11223344scan_led1000
- Quartus环境下的1000进制计数器的扫描显示电路-Quartus environment under the 1000 counter-band scanning display circuit
23565785scan_led
- Quartus环境下的7段扫描显示电路的源程序-Quartus environment of the seven scanning display circuit of the source
55478362cntshow
- Quartus环境下的12进制计数器的扫描显示电路-Quartus environment of the 12 counter-band scanning display circuit
123424475SINGT
- Quartus环境下的正选信号发生器的实验源码-Quartus environment is the election of signal generator FOSS
234352325DECL7S
- Quartus环境下的7段译码管的扫描显示电路-Quartus environment of the seven decoding of the scan show circuit
ddsquartus
- 使用QUARTUS 2编译的DDS的源码-QUARTUS use two compiled the DDS source
ASYfifo
- 这是FIFO程序，开发工具是ISE或QUartus。-procedures, development tools or QUartus ISE.
fir_finall
- 用verilog编写的fir滤波器程序，开发环境可以用ise quartus或active hdl等-verilog prepared with the fir filter process development environment can be used ise quartus or other active hdl
jicifenpinqi
- 别人编写的奇次分频器，用VHDL写的，我已经在QUARTUS上验证过了-others prepared by the odd dividers, VHDL write, I have QUARTUS tested the
nios_uart
- 基于Nios II的串口通信，在quartus的开发环境中进行的实验-based Nios II Serial Communication in quartus development environment for the conduct of the experiment
38encode
- 三八译码器的源代码，在quartus II 6.0中进行进行设计的，有vhdl源代码-March 8 decoder source code, in quartus II 6.0 for the design, Source code is vhdl
SVGA_quartus
- 在开发板上实现svga条形信号发生器的源代码，是在quartus II 6.0的开发环境中运行的-achieved in the development of board svga strip signal generator source code, in quartus II 6.0 development environment running on
656to601
- 本程序实现视频图象的CCIR656转换CCIR601格式,使用的环境是Quartus II 4.0-the program CCIR656 video image conversion CCIR601 format, The environment is the use of Quartus II 4.0
lcd4quartus
- 128×64单色点阵LCD的quartus工程文件-128 x 64 monochrome dot-matrix LCD quartus works documents
3des-VHDL
- 3des的VHDL实现，适用于quartus环境-3des VHDL applicable to the environment quartus