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AlteraQuartusII6.0crack
- Altera Quartus II 6.0 破解文件-Altera Quartus II 6.0 crack documents
fcout
- 频率计源代码,性能很好,verilog写的,顶层原理图,底层语言写的,效果很好,开发环境为quartus-Cymometer source code, good performance, verilog written by the top diagram, the bottom language was written. good effect, and development environment for quartus
2FSK2psk
- 2FSK2PSK-二进制频移键控和相移键控信号发生器的源程序,是基于QUARTUS II软件平台,使用VHDL语言-2FSK2PSK-binary frequency shift keying and phase shift keying signal generator source, QUARTUS II is based on the software platform, the use of VHDL
q2_7_license
- altera quartus 2 7.0 许可文件-altera quartus 2 7.0 permit documents
suij
- 硬件编程实现伪随机交织器和随机交织器,应用环境Quartus II5.0-hardware programming pseudo-random interleaver and random interleaver, application environment Quartus II5.0
quartusGuide
- 设计输入 ! 多种设计输入方法 – Quartus II • 原理图式图形设计输入 • 文本编辑 – AHDL, VHDL, Verilog • 内存编辑 – Hex, Mif – 第三方工具 • EDIF • HDL • VQM – 或采用一些别的方法去优化和提高输入的灵活性: • 混合设计格式 • 利用LPM和宏功能模块来加速设计输入-design inpu
Quartus_vhdl
- 用QUARTUS编译通过的等精度频率计,我错误,但有几个警告(不影响设计)。我的毕业设计啊!!! -QUARTUS used by the compiler, and other precision frequency, I am wrong. But there are several warning (not affect design). I graduated from the design ah! ! !
b8bit_adder
- 8位的加法器设计,分4个工程完成的,用的是Quartus II软件。-eight of the adder design, four hours to complete the project, using the Quartus II software.
shuzilvboqideyingjianshixian
- 数字滤波器的硬件实现,里面实例可以直接在quartus中运行-Digital Filter hardware, which can be directly examples run in quartus
IIS_VHDL
- VHDL实现了IIS接口程序,在Quartus II 6.0上编译通过,在板子上可以读取IIS数据-IIS VHDL interface procedures, the Quartus II 6.0 compiled by the board can read data IIS
circularbuffer
- Circular_Buffer,流水线型多位缓存器,verilog语言描述。通过modelsim 6。0仿真,quartus 综合通过。
89_full_adder
- full adder设计代码,verilog 语言描述,通过modelsim 仿真,quartus综合
tcl_io
- quartus 中,自己写的tcl,分配io的例子。
io-sortation
- quartus 中,高级io分配,手动的例子
GuangShanChi
- 光栅尺的四细分和辩向电路,并具有计数器功能,利用Quartus综合,可以参考
VH_SYN
- 标准电视信号的同步生成程序,利用VHDL和原理图,利用Quartus综合
leon3-altera-ep2s60-ddr
- This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOT
SignalTapII
- Altera公司Quartus II软件的逻辑分析使用流程,中文版本。该文件详细说明了使用SingalTapII的流程和基本使用方法,对使用FPGA的人有很大帮助。
srbjq
- quartus环境下开发的三人表决器(三种不同的描述方式)maxplusII兼容
Crack_QII71_b156
- Quartus v7.1的key_gen b156破解器