搜索资源列表
equivalent_sample
- 基于FPGA的等效采样系统设计，包含状态机设计，双口ram使用方法，分频设计等-FPGA-based equivalent sampling system design, including the state machine design, dual-port ram usage, frequency design
adc0809
- 利用FPGA控制ADC0809采样电压，并通过数码管显示电压数值-ADC0809 FPGA control by sampling the voltage and the voltage value through the digital display
PLD-LOGIC_SPWM
- 电子设计竞赛中获二等奖，在FPGA中实现的两路自然采样SPWM，原理图输入法设计，1024*八位正弦查找表，带FSK和ASK调制功能，频率范围8KHz~12KHz.-Electronic Design Competition second prize in the FPGA to achieve the two natural sampling SPWM, schematic design input, 1024* eight sine look-up table, with FSK and A
adc
- 设计ADC控制器，Verilog代码.利用有限状态机设计方法在FPGA上设计ADC0809的接口控制器，采样结果送到数码管显示出来。-ADC controller design, Verilog code using finite state machine design in the FPGA design ADC0809 interface controller, the sampling results to the digital display.
state_FPGA
- 基于FPGA的状态机，应用于高速A/D采样上，通过测试-FPGA-based state machine, used in high-speed A / D sampling, the test
my_adc1
- 020单片机ADC1采样程序；额外功能：main中主要实现与FPGA并口通信，总体实现FFT,不过FPGA部分没有上传，因此能实现的是ADC1采样。-020 SCM ADC1 sampling procedures additional features: main key to achieve in parallel with the FPGA communication, achieving an overall FFT, but the FPGA portion not uploaded
dso
- 基于fpga的简易数字存储示波器设计，包含采样，检测触发，波形存储等模块功能-Fpga-based design of simple digital storage oscilloscope, including sampling, testing the trigger, waveform storage module functions
ADSample_FPGA
- 开发环境为QuartusII。这是AD采样的verilog代码部分，在FPGA上硬件实现AD采样的一部分功能-Development environment for the QuartusII. This is the verilog code for part of the AD sample, the FPGA hardware on the part of the function AD sampling
yinpinfangda
- 采用基于FPGA的频域加窗与反傅立叶变换的数字幅频均衡功 率放大器:此方案采用高速FPGA，以及配套的高速AD、DA 对信号进行采样，傅 立叶变换，在频域上对信号进行加窗操作，然后通过傅立叶反变换将波形还原。 以得到需要的频谱幅度。-FPGA-based frequency domain using the windowed Fourier transform with the number of pieces of anti-band equalizer amplifier: Th
adc_cvt
- FPGA控制AD采样一个周期采样32点，求给改成64点-FPGA controls the sampling period 32 AD sampling a point, seeking to change the 64-point
PAPER
- 基于FPGA的高速并行A_D采样控制电路的设计-AD high speed sampling circuit design based on FPGA
adcint
- 基于FPGA，实现控制ADC0809对模拟信号的采样输出-Based on FPGA, to control the ADC0809 to the analog signal sampling output
ADC_TLC549
- 利用FPGA控制tlc549实现采样，并通过数码管显示采样结果-Implementation using FPGA control tlc549 sampling, and sampling results through digital display
DataRecovery
- 利用过采样技术，适用于FPGA对百兆左右的突发数据进行恢复-FPGA can recover burst 100MHz data based on over sampling
ADc
- 与单片机相比，用CPLD/FPGA器件更适合于直接对高速AD采样控制。本实验接口器件为ADC0809，根据ADC0809的工作时序使用CPLD产生该控制信号，CPLD启动AD转换后，得到的数据送至单片机并在PC机及数码管上显示AD转换结果。-Compared with the microcontroller, CPLD/FPGA devices more suitable for direct sampling control of high-speed AD. The interface of
Temperature_acquisition
- 用VHDL语言在FPGA上实现了8路温度数据的采样功能。控制THS1408芯片进行AD转换，采样后存入对应的8组寄存器，并产生使能信号通知其他模块进行8路数据的统一采样。-8-channel temperature data sampling function is implemented on FPGA using VHDL language. Control THS1408 chip AD converter, and sampled into the corresponding set o
ad_da
- Altera FPGA ad采样，da回放-Altera FPGA AD sampling, da playback
AD250MdaFIFO
- AD250 FPGA PCI桥采样示例代码-AD250 FPGA PCI bridge sampling
AD7656
- AD7656芯片的FPGA接口程序，实现AD采样和数字信息转换-AD7656 chip FPGA interface program, the AD sampling and digital information into
uart
- 用FPGA实现串口的收发功能，采用16背波特率的时钟对RXD采样，波特率的误差允许范围为4.8 -16 back baud rate clock on RXD serial transceiver functions FPGA implementation sampling, the range of allowable error of the baud rate of 4.8