搜索资源列表
SDRAM
- verilog编写的SDRAM实验,有串口调试助手和相关资料-Verilog prepared by the SDRAM experiment, a serial debugging assistant and related information!!!!!!!!!!!!!!!!!!!!!
DDR3-SDRAM-Verilog-Model
- ddr3模型以及代码和测试程序,不过带有小瑕疵-ddr3 model and code and test procedures, but with small flaws
sdram
- verilog sdram读写控制,实现数据存储于发送-sdram read and write,data store and communication
SDRAM
- 用Verilog写的SDRAM测试程序。先向SDRAM里面写数据,然后再将数据读出来做比较。-Written using Verilog SDRAM test program. Xianxiang SDRAM write data inside, and then read out the data for comparison.
sdram_singale_word
- 使用verilog驱动的sdram单字节读写,可以学习一下sdram最基本的功能,学习sdram参考程序。-Use sdram verilog-driven single-byte read and write, you can learn the most basic functions sdram, sdram reference learning program.
SDRAM_interface
- SDRAM verilog 代码,已经在MT48LC1M16A1上验证过。-The MT48LC1M16A1 is a 16Mb SDRAM arranged in 1M x 16bits. 1. the SDRAM has been initialized with CAS latency=2, and any valid burst mode 2. the read agent is active enough to refresh the RAM (if not, add a re
sdram
- FPGA读写SDRAM。里面有详细的注释,供初学者参考,Verilog 语言-FPGA read SDRAM. There are detailed notes, reference for beginners,
SDRAM-controler-based-on-the-FPGA
- 本例是用FPGA器件实现SDRAM操作,所用语言为verilog硬件描述语言,希望可以对学习FPGA的人起到帮助作用-In this case is to achieve SDRAM operating with FPGA devices, and use of language verilog hardware descr iption language, I hope people can learn to play FPGA helpful
DDR-SDRAM-Controller
- DDR SDRAM控制器verilog代码及中文说明文档-DDR SDRAM Controller Using Virtex-5 FPGA Devices
1-SDRAM
- 串行接口是最简单的一种通信方式,串口通信有两种方式,一种是同步串行,如SPI接口;另一种则是异步串行,即我们所说的UART。这个项目向大家展示了如何使用FPGA来模拟UART收发器。-uart fpga verilog
SDRAM
- sdram 状态机驱动源程序工程 完全使用verilog hdl写的-sdram state machine driver source project written entirely in verilog hdl
S27_SDRAM_IP
- SDRAM 驱动读写demo,用verilog写的上板测试过-SDRAM verilog
SDRAM-and-FIFO-for-DE1-SoC-master
- Verilog TUTORIAL for beginners. We had earlier published a Verilog tutorial that made use of the Xilinx ISE Simulator.
verilog-SDRAM
- 用verilog语言写的SDRAM读写控制器的程序,经测试有效。-Written in verilog language SDRAM read and write controller procedures, the test is valid.
DDR3 SDRAM Verilog Model
- ddr3的逻辑带么参考,有需要的可以看一下。。。。。。。。。(ddr3 ssscoede code code code)
4NandFlash
- 控制器顶层,以及实现功能模块简单的snandflash_top_ctrler(Simple nand_flash_top_ctrler)
sdram_verilog
- verilog实现外部sdram读写功能,实测可用(SDRAM read and write function by verilog)
sdram_ip
- 完成SDRAM的上电配置,状态机编写其读写模块,存储模块,并通过两个异步作为存储和读取的通道(Complete the SDRAM power-on configuration, the state machine to write its read-write module, memory module, and through two asynchronous as a storage and read the channel)
my_sdram_mdl
- 此功能为altera fpga 的sdram 控制器,串口接收与发送(This feature altera fpga sdram controller, serial port to receive and send)
FPGA_SDRAM
- 基于Verilog语言的SDARAM代码(SDARAM code based on Verilog language)