搜索资源列表
DDC_FilterChain_HDL.zip
- simulink demo of ddc,simulink demo of ddc
pll.rar
- 模拟锁相环（apll）的一些simulink模型,Analog phase-locked loop (apll) some simulink model
DES
- DES加密算法的VHDL实现,采用流水线技术实现-The VHDL implement of DES encrypt algorithmic
Freq_Divider
- frequency divider using verilog
HDLImplementationoftheVariableStepSize
- proposes a Verilog implementation of the Normalized Least Mean Square (NLMS) adaptive algorithm, having a variable step size. The envisaged application is the identification of an unknown system. First the convergence of derived LMS algorithm
proiect
- Fir filter implemented in verilog and tasted. also conteins the implementation in simulink
BPSK_receiver
- BPSK接收机设计，能够通过Synplify DSP直接生成Verilog代码。-BPSK Reciver model. This simulink model can generate RTL code via Synplify DSP.
dct2d
- 2D-DCT, 二维离散余弦变换模型。能够通过Synplify DSP生成Verilog代码 -2D-DCT model. This simulink model can generate RTL code via Synplify DSP.
PC-CFR
- 采用matlab simulink编写的消峰参考设计，可以直接生成verilog代码。消峰主要用于降低无线信号的峰均比，提高功放效率。-Clipping prepared using matlab simulink reference design, you can generate verilog code directly. Consumers peak mainly used to reduce radio signal PAR, improve power amplifier effic
verilog
- this is another impact to the simulations
FpgaFskMod
- 基于verilog的2FSK调制程序，simulink仿真通过(2FSK modulation program based on Verilog, Simulink simulation passed)