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SPI.rar
- 新华龙单片机SPI通信代码经过测试，保证能用，包括SPI存储器读写，主从模式通信,New single-chip SPI communication code hualong tested to ensure the use, including memory read and write SPI, master-slave mode of communication
spi
- SPI master的verilog代码-Verilog code for SPI master
spi
- SPI总线接口的verilog源码，包含仿真模块modelsim 和 quartus 工程。本人测试通过。-SPI bus interface in verilog source code, including the simulation module modelsim and quartus project. I test.
FPGASPI
- 用FPGA实现主SPI程序,包含开发工程、测试文件和源文件代码-fpga design the SPI code
pwm16bits
- SPI总线Master的verilog代码-SPI Bus Master of Verilog code
spi.tar
- This is a verilog code used oversampled clock to implement SPI slave. Also include C code for a ARM processor as the SPI master-This is a verilog code used oversampled clock to implement SPI slave
LPCSPIMaster
- This file as the Master code for LPC2148 master SPI communication
ComunicacaoSPI_Master
- atmega16 spi master code
F04x_SPI0_Master
- C8051F040 SPI Test Code (master unit)-C8051F040 SPI Test Code (master)
SPI
- 这是MC9S12DG128单片机SPI通讯模块开发实例,该实例包含SPI主从机的全部源代码,可实现双机通讯。-This is the MC9S12DG128 MCU SPI communication module development instance of SPI master and slave machines with all the source code, enabling two-machine communication.
spi_verilog
- 实现SPI MASTER功能，并有仿真代码和仿真结果。-To achieve SPI MASTER function, and a simulation code and simulation results.
SpiMaster
- This a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile and simulate-This is a verilog code for SPI Master testbench is also provided spi_top.v Xilinx ISE or Icarus verilog to compile an
spi_master
- 用VHDL编写的一个SPI主机程序，SPI模块采用最常用的模式0方式（即CPOL=0,CPHA=0）通信。文件内含测试文档，已在Modelsim6.5上测试通过，可在FPGA上直接调用。-A SPI Master code edited by VHDL language,the SPI modul use 0 MODE(i.e CPOL=0,CPHA=0)to communicate with the SPI Slave.and there is a testbench in the file
SPI-Master
- CSPI MASTER CONTROLLER CODE SOURCE
SPI
- SPI master code for microcontrollers
SPI
- spi master code for fpga quartus altera
SPI-verilog
- spi master code for fpga quartus altera
SPI-Master-Core-DAC-ADC-spartan
- SPI Master Core for spartan (ADC, DAC) vhdl code
spi-fpga-master
- SPI Master code for use in fpga programming. the code model spi communication protocol.
spi_verilog_master_slave_latest.tar
- spi 的verilog rtl 代码, 包括整体仿真环境，测试码等(spi master or slave verilog rtl code)