搜索资源列表
dac7554
- dac7554控制模块，包含简单的testbench和debussy的仿真波形文件。-dac7554 control module contains a simple simulation testbench and debussy waveform files.
SDRAM_Modelsim
- 基于VHDL的SDRAM控制器源代码以及modesim验证工程的testbench-SDRAM controller based on VHDL source code and modesim verification testbench works
one-key-multifunction_verilog
- 采用FPGA来实现的一键多能算法，Verilog 编码，包含testbench，有详细的解释说明。-Using FPGA to implement one key multifunction algorithm, Verilog coding, including testbench, a detailed explanation.
DDR3-SDRAM-Controller
- DDR3的控制器（并带有Testbench），可烧录到FPGA中对内存进行读写，相关技术人员可在该代码上修改用于其他场合-DDR3 controller (with an Testbench), the FPGA can be burned to the memory read and write, the relevant technical staff can modify the code to be used on other occasions
Chapter-7
- 7.2 I2C Master Controller设计 7.3 I2C Master Controller Testbench设计-7.2 I2C Master Controller Design 7.3 I2C Master Controller Testbench Design
Chapter-8
- 8.2 CAN Protocol Controller模块设计 8.3 CAN Protocol Controller Testbench设计 -8.2 CAN Protocol Controller Module Design 8.3 CAN Protocol Controller Testbench Design
Chapter-12
- 12.2 ATA主机控制器设计 12.3 ATA主机控制器Testbench设计 -12.2 ATA host controller design 12.3 ATA host controller Testbench Design
Chapter-13
- 13.2 RISC-CPU设计 13.3 RISC-CPU Testbench设计-13.2 RISC-CPU design 13.3 RISC-CPU Testbench Design
CRC_Tst
- 关于CRC的发射，以及接受的验证，用Verilog实现，包含testbench验证-About CRC launch, as well as acceptable verification, using Verilog implementation, including verification testbench
pr_step7-(1).vhdl
- 8位alu 附上testbench以供仿真-8 alu attach testbench for simulation
ethenete
- 基于verilog的三速以太网源程序，文件中包含源程序和测试程序。-tri_model ethernet source code based on vhdl languange, include source code and testbench in the file.
ALU
- 简易的VHDL程序，主要实现ALU的逻辑功能，进行选择和数据的移动。很适合初学者对VHDL的理解。内含有testbench可以进行Qutarus的仿真-Simple VHDL program, the main achievement of the ALU logic functions, to select and move data. VHDL is suitable for beginners to understand. Containing a simulation testbench
DCT_IP_Testbench
- 一个DCT变换的完整IP，基于Verilog编写，同时包括完成的testbench，方便模块的仿真和测试。-DCT transform a complete IP, based on Verilog prepared, including both complete testbench, convenient module simulation and testing.
dac7564
- 基于VHDL的dac7564驱动程序和该程序的testbench测试程序-I DON T KOWN
lab-assignment1
- 这个是计算机结构的实验内容,主要包括逻辑门的设计(例如:与门,或门,非门).此外还有testbench的设计代码.-This is a computer architecture in experiments, including the design of logic gates (for example: AND gates, OR gates, NAND gate). Addition testbench design code.
yimaqi_beh
- 8位计数器作业中的behavioral描写，没有带testbench，已经通过-1. Construct VHDL models for 74-139 dual 2-to-4-line decoders using three descr iption types, i.e., behavioral, dataflow and structural descr iptions. Synthesize and simulate these models respectively in the en
8051core-Verilog
- 基于Verilog的 8051 IP核 内含 Testbench-The 8051 IP core based on Verilog
乘法器
- 乘法器的源代码，以及其测试文件，testbench，是word的形式
spi_vmm1.2
- VMM1.2的SPI示例代码，介绍各个验证组件的功能和用法。Verilog编写，使用VCS仿真-The example SPI testbench code of the VMM1.2
tb_asy_fifo
- the testbench of asynchronous fifo-test the logic function of asynchronous fifo