搜索资源列表
uvm_switch_8
- 使用uvm验证环境搭建的testbench，主要验证switch的功能。可以学习uvm的简单功能-use uvm set up testbench ,the mainly focuse is verification swtich,you can learning uvm sample fucntion
cpu
- 该源码为之前上传的allcpu 的仿真代码testbench，使用modsim进行仿真。-The source code for previously uploaded allcpu simulation code testbench, use modsim simulation.
ram_test
- ISE中双端口不同位宽ram的数据存储，包括testbench-veirlog ram FPGA
CMOS_proj2_RTL
- 用上位机UART控制一个十字路口的交通灯的.v文件。包括testbench在内，可用FPGA cycloneII DE270跑仿真。-traffic lights at a crossroads. V file controlled by PC UART. Including testbench , available FPGA cycloneII DE270 run the simulation.
Fsm
- 基于verilog的FSM设计，设计“101001”的序列检测器；包括testbench文件-The FSM based verilog design, design " 101001" sequence detector including testbench files
dff-n-d-latch
- Dlatch and D Flipflp code with testbench in Verilog
hamming
- 32位海明码编码解码的vhdl代码，有testbench验证。-32 Hamming code encoding and decoding of vhdl code, testbench verification.
mcu8051
- 一个实现MCU51处理器的完整VHDL源代码，包含testbench-An implementation MCU51 processor complete VHDL source code, including testbench
cordic_1-0
- 关于cordic算法的C MODEL实现，包括几种不同的模式，如求模值、求相角，求COS,SIN函数等。程序还包括TESTBENCH测试程序。-About cordic algorithm C MODEL implementation, including several different modes, such as modulus values, seeking phase angle, seeking COS, SIN function and so on. TESTBENCH test
ise_c8051
- r8051（c8051）IP源码，使用VHDL编写。整个工程通过ISE13.2实现，附带完整testbench，并实例化了rom和ram，可以运行c代码。工程内包含modelsim的仿真脚本，可以观测程序运行时的内部硬件工作情况。-r8051 (c8051) IP source code, the use of VHDL. The whole project is realized by ISE13.2, with complete testbench, and examples of the
simu01
- spartan 3 series ADC vhdl code testbench
24
- 基于6M晶振FPGA的篮球24秒计时器verilog HDL代码，附testbench-Verilog HDL code for FPGA-based 6M crystal basketball 24 seconds timer, with testbench
adder
- 包含32位有无符号数的加减法，verilog语言描述，加法器分别采用行为级描述、行波进位、平方根进位三种描述方法，并有简单的testbench-32bits adder with addition and subtraction function. verilog HDL language . three kinds of implementations: adder behavioral descr iption, ripple carry, the square root of the ca
syncram
- verilog rtl and testbench code for single port sync ram
lzrw1-compressor-core_latest.tar
- Lzrw1 压缩算法。spatan6上运行，有完整的仿真环境和代码testbench-Lzrw1 compression algorithm. runs on spatan6, a complete simulation environment and testbench code
counter8
- 八位计数器，带有是使能键和重置键。附带testbench.-8 bit counter
counter8
- 8 位 计数器，带使能键和重置键。附带testbench, verilog 环境-8 bit counter
traffic_tb
- verilog， 铁路道口异步交通灯设计的testbench.-testbench for an asynchronous circuit that is to control the gates and red flashing light at a railway level crossing,
SPI-Core_nguyen
- SPI Master Core HDL: VHDL 93 Compatibility: all FPGAs, CPLDs parameterization: - variable data width - Phase/polarity configurable - selectable buffer depth - serial clock devision due to system clock package usage: IEEE
radix2_8fft
- 基2_8点fft运算的程序，带testbench，可以直接仿真使用,程序是分模块设计的。-2_8 point fft program based computing with testbench, you can use the direct simulation.