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lunwen
- 潘明海 刘英哲 于维双 (论文) 中文摘要： 本文讨论了一种可在FPGA上实现的FFT结构。该结构采用基于流水线结构和快速并行乘法器的蝶形处理器。乘法器采用改进的Booth算法，简化了部分积符号扩展，使用Wallace树结构和4-2压缩器对部分积归约。以8点复点FFT为实例设计相应的控制电路。使用VHDL语言完成设计，并综合到FPGA中。从综合的结果看该结构可在XC4025E-2上以52MHz的时钟高速运行。在此基础上易于扩展为大点数FFT运算结构。 -Pan Mingha
RS_FPGA_papers
- 两篇RS编码fpga仿真的硕士论文，看完会对RS编码及其硬件实现步骤有清晰的理解。-2 RS codes fpga simulation master' s thesis, after reading the RS coding and hardware implementation will have a clear understanding of the steps.
Desktop
- 基于FPGA的频率计设计 源代码+论文 绝对好用-The frequency meter design based on FPGA source code+ thesis
Vedio_FPGA
- 基于FPGA和SOPC的视频图像处理，视频编解码，系两篇硕士论文，其中一篇需要用CAJ阅读器打开-FPGA and SOPC based on video image processing, video codec, two master' s thesis, Department, of which a reader needs to open with CAJ
DSPFPGA
- 交大一个DSP和FPGA的电机项目的硕士论文，非常实用 -Jiaotong University, a DSP and FPGA motor master' s thesis project, very useful
QAM_blind_equalizer
- 硕士论文，主要讲解应用QAM系统的盲均衡自适应算法的仿真及FPGA实现。-Master s thesis about blind Equalization for QAM systems
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- 基于FPGA 的数字接收机设计方案，别人的硕士论文，个人认为较好-FPGA-based digital receiver design, someone else' s master' s thesis, think better
aes-encryption
- 为实现AES加密设计的高速实现，本设计引进了一种AES的并行设计算法，整体结构和加密进程，基于FPGA本身的特征和算法，设计使用并行处理算法来实现并行处理进程。-To implement the design of the AES algorithm with a high speed, the thesis introduce the principia mathematica of AES algorithm, integral structure and the Encryption pr
pmsmbased-onFPGA
- 基于fpga的永磁同步电动机的矢量控制教程，硕士论文-Fpga-based vector control of permanent magnet synchronous motor tutorial Thesis
wavelet-denoise
- FPGA实现小波阈值降噪的算法说明，有大量的硕士论文，很有参考价值，基于这些资料可以写出源码。-FPGA realization of wavelet threshold noise reduction algorithm descr iption, there are a lot of master s thesis, a good reference, based on these data can be written source.
impo_these_FPGA_SAPTONO_DEBYO_00_00
- this document is a thesis discuss about fpga implementation of signal processing system on targets such as altera and xilinx
verilog-radix4
- Master Thesis(FFT_RADIX-4)-This thesis deals with a 64-point Radix-4 in-place FFT, based on an improved FFT algorithm. The whole FFT structure was implemented based on self-designed modules and by manipulating the embedded Virtex II FPGA’s module