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graph, heap, sorting, timing source code
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graph, heap, sorting, timing source code
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verilog hdl FPGA vga时序显示经典源程序 很实用的-verilog hdl FPGA vga display timing source
code very useful
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AT24C512采用IIC串口总线方式进行数据传送,读写数据的时序源代码!-AT24C512 way with IIC serial bus data transfer, read and write data timing source code!
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AT24C04采用IIC串口总线方式进行数据传送,读写数据的时序源代码!-AT24C04 way with IIC serial bus data transfer, read and write data timing source code!
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This a simple position location algorithm using Least Square Estimation algorithm. Timing information is time of flight (TOA) of signal between Tx and Rx. This code generally describes the Positioning method, Also it plots final coordinate of node in
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包含定时关机、进程管理。关机前先结束指定进程。-Timing shutdown, shut down before the end of the specified process.
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FM24C64采用IIC串口总线方式进行数据传送,读写数据的时序源代码!-FM24C64 way with IIC serial bus data transfer, read and write data timing source code!
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使用 FPGA 控制 VGA 显示
相关知识介绍:包括 显示器术语
显示卡术语
VGA 时序设计
色彩原理
显示
源代码
相关测试图片-The use of FPGA control VGA display relevant knowledge, Introduction: terminology, including display graphics card design color theory terminology VGA timing related t
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高楼电梯自动控制系统(Windows平台上运行的ispLEVER编程软件。
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1统控制的电梯往返于1-9层楼。
2客要去的楼层数可手动输入并显示(设为A数)。
3梯运行的楼层数可自动显示(设为B数)。
4A>B时,系统能输出使三相电机正转的时序信号,使电梯上升;
当A<B时,系统能输出使三相电机反转的时序信号,使电梯下降;
当A=B时,系统能输出使三相电机停机的信号,使电梯停止运行并开门;
5是上升还是下降各层电梯门外应有指示,各层电梯门外应有使电
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hc11 timing source code and simulation in Verilog program
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This is the source code of interface programming of Timing in Linux Platform
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定时排插源代码,基于C51单片机编写的,可以定时到1分,用4位数码管作显示。-Timing strip source code, written in C51 microcontroller-based, can be timed to 1 minute, 4-digit LED for display.
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基于dspTMS320C5402的定时器实现定时的源代码(在ccs3.3软件环境下)。-Based on the dspTMS320C5402 timer timing source code ( in CCS3.3 software environment ).
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基于最小二乘法实现精确到采样点间的准确定时,性能远远高于双程测距方法实现的测距与定时。仿真表明此方法对于抗噪声和频偏具有很好的作用。这是源代码,用matlab编写,项目要求实现10ns的精度实际中我们实现了3ns以内的精度。-Based on least square method to achieve precise sampling points of accurate timing between, performance is much higher than the round tri
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VerilogHDL做的关于模数转换芯片MCP3202时序源代码,及其ModelSim仿真文件-VerilogHDL do the analog-to-digital conversion chip MCP3202 timing source code, its ModelSim simulation files
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Vc++ 最近开发的源代码定时关机小程序,只是出于兴趣,和大家分享一下。-Vc++ recently developed source code timing shutdown of small procedures, just out of interest, and we share.
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vb定时关机源代码,可以设定一个时间,时间一到该程序就将关掉电脑-vb source code off timer, you can set a time, the time to turn off the computer the program will
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This Variable Font varies in size with respect to its Timing Source Code for Linux.
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FPGA控制SRAM读写时序源码,代码桂发,新手一看就懂-FPGA control SRAM write timing source code Guifa novice understand at a glance
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