搜索资源列表
USB.rar
- 用VHDL实现的USB IP核，大家可以参考下,Use VHDL to achieve USB IP core, we can refer to the following
usb11.rar
- 基于verilog HDL的一个USB 1.1的IP 核，内有详细文档说明。,Verilog HDL based on a USB 1.1 of the IP core, which has detailed documentation.
usb20_ipcore_usb_funct
- usb的芯片ip core. 用HDL描述，适合asic/fpga人员参考或使用。USB ip core for ASIC/FPGA designers.-usb chips ip core. with HDL descr iption suitable for asic/fpga staff reference or use. USB ip core for ASIC/FPGA designers.
USBipcore
- usb1.1 ip核，使用verilog编写-usb1.1 ip nuclear, prepared using the Verilog
usb
- USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control,
slaveController
- 对USB的从机设备的IP核进行了重新设计并在一定程度上进行了优化-On the USB device from the IP core has been redesigned to some extent, is optimized
RTL
- 对usb设备控制的ip核进行了重新设计并进一步优化-Usb device on the control of nuclear ip has been redesigned and further optimize
usbdetect
- 检测 IP 网络上远端计算机上是否有 USB 设备插入的。Server.c 和 Client.c 分别用于本机和远端机。也可以设为 127.0.0.1 在本机测试运行两个程序。-Remote USB device detection over ip network. Client.c and Server.c are for local and remote machines respectively.
usb_funct
- usb 2.1 IP 的 东西 很好的 是 我的 -usb2.1 IP it s so eay to me to you
usb_latest.tar
- 用VHDL语言编写的USB 2.0IP核。USB 2.0的传输速率是高速率480 Mb/s，需要再外扩一个PHY。-This is a USB 2.0 compliant core，USB 2.0 allows data transfers of 480 Mb/s. Because of the high interface speed, an external PHY will be required with this core.
usb
- USB完整代码 包括vhdl和verilog两种-usb ip core
TSMC_DSD-USB-IP
- TSMC USB IP Spec for 0.18um proce-TSMC USB IP Spec for 0.18um process
ISP1362-IP
- ISP1362的IP核用在USB 控制上可与PC通讯，作为SOPC的IP核-ISP1362' s USB IP core used in the control of communication with PC as the IP core SOPC
verilog-usb--protel-design
- 基于FPGA的usb2.0 ip核设计，所用的语言是verilog-FPGA-based usb2.0 ip core design, the language used is the verilog
USB-1.1-IP-CORE-VHDL
- USB1.1标准接口的IP核的实现和其设计实现的源码范例VHDL-USB1.1 standard interface IP core implementations and examples of their design and implementation of the VHDL source code
usb
- USB的verilog IP模块，经过DesignCompiler综合验证-USB-verilog IP module, comprehensive verification through DesignCompiler
nop-usb-xceiv
- linux系统上，NOP所有USB收发器，USB收发器内置到USB IP程序。-linux system, NOP USB transceiver, USB transceiver built into the USB IP program.
FPGA IP cores
- FPGA IP cores on verilog for USB CY7C68013, VGA, Ethernet DM9000A, Sound WM8731.
USB-IPcore-Verilog
- USB IP 核设计，Verilog，ISE工程可以打开-USB IP core design, Verilog, ISE project can be opened
usbip-win-master
- USB/IP emulator for windows 10 x64