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USB 1.1 IP-CORE和设计范例 VHDL源代码
- USB 1.1 IP-CORE和设计范例 VHDL源代码-Sample program for USB1.1 IP core design, VHDL source code
USBipcore
- usb1.1 ip核，使用verilog编写-usb1.1 ip nuclear, prepared using the Verilog
usb_doc
- USB_DOC,详细描述了usb1.1协议-USB_DOC，it descibes usb
IPcore
- 非常有用的IP核资源，里面包含了JTAG,MEMORY,PCI，SDRAM和USB1.1等内容，期望对大家有用-A very useful IP core resources, which includes the JTAG, MEMORY, PCI, SDRAM, and USB1.1 and other content, expectations for all of us
usb11_phy_translation_latest.tar
- USB1.1 物理层实现 VHDL，opencore上也是可以下载的，是1.1的版本，比较简单，但是很实用，对于入门usb还是有帮助的-usb11_phy_translation_latest version
USB-1.1-IP-CORE-VHDL
- USB1.1标准接口的IP核的实现和其设计实现的源码范例VHDL-USB1.1 standard interface IP core implementations and examples of their design and implementation of the VHDL source code
usb_Phy
- usb1.1 VHDL源码，主要描述收发数据过程-usb1.1 the VHDL source code, descr iption of the send and receive data process