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EPM240_Uart
- 基于Quartus II的Verilog编写的Uart串口测试程序。数据收发机LED灯测试。-Based on the Verilog Quartus II prepared Uart serial port test program. LED lamp test data transceiver.
uart_nbit
- 用verilog语言写的串口通信程序,包括收发两个模块,可用于FPGA的通信中,可通过程序设置收发的位数,有很好的扩展性.-Verilog language used to write serial communication program, including the sending and receiving two modules can be used for FPGA communications, you can send and receive through the progr
uart
- 自己写的Verilog写的串口程序,实现收发功能。方法不错,可以参考下。-verilog...uart...
uart
- verilog实现的按键控制的串口简单收发通信-verilog implementation simple keypad control, serial communication transceiver
chuankoumokuai
- 用VERILOG实现的串口RS232自收发模块,以通过板级测试。-RS232 serial port with the VERILOG achieve self-transceiver module, through board-level test.
rs232
- 这是用verilog语言写的串口自收发实验的源代码,通过板子实验,采用分层模块化设计,代码大家请仔细阅读-It is written in verilog serial transceiver test from the source code through the board experiments, a stratified modular design, code, we can slowly digest
task22constant
- 清华大学电子课程设计:Verilog语言,Quartus可以正确运行,下载到FPGA上可完成PC与FPGA一串数据的连续收发,且实现本地回环,异步串口通信-Verilog language, Quartus can be correctly downloaded to the FPGA to be completed by PC and FPGA transceivers continuous string of data, and implement local loop, asynchron
uart_1203_4
- MUC+fpga 串口扩展,已调试通过,4路串口共用中断,收发fifo,波特率可调,其他的可以自己添加,网上类似资料极少,极具参考价值!只提供verilog源码!-MUC+ fpga McU.that, already debugging, through, 4 road serial common interrupt, receiving and dispatching fifo, baud rate can be adjusted, the other can add your own, o
iic_com
- 用verilog语言实现IIC读写与并通过UART协议在串口PC显示,实现数据收发-IIC using verilog language and literacy with the PC via the serial port UART protocol display, data transceiver
UART
- FPGA实现串口的收发,可以改波特率。Verilog HDL语言-FPGA Verilog HDL
fpga_uart
- verilog编写的简单串口收发代码,quartues II 下cyclone II 测试通过-prepared by the simple serial transceiver verilog code, quartues II test under the cyclone II
CHUANKOUrxtx
- Verilog写的串口收发程序 ,基于FPGA的相关测试,亲测没有任何问题。-Verilog write the serial transceiver procedures, FPGA-based correlation test, pro-test without any problems.
UART01
- 可靠的FPGA串口收发程序,用Verilog编写,可以自行调整波特率!-Reliable FPGA serial transceiver procedures, with Verilog prepared to adjust the baud rate themselves!
string
- 用verilog语言实现串口收发器设计,有详细代码-Serial Transceiver Design verilog language, a detailed Code
verilog_UART
- verilog语言 FPGA 串口收发模块,既可以接收也可以发送,可以自行更改波特率-Verilog language FPGA serial transceiver module, I can receive can send also to change the baud rate
uartverilog
- 自动收发的verilog编写的uart串口程序-Automatically send and receive serial uart verilog written procedures
EP1C3-uart_1_verilog
- EP1C3-uart_1_verilog,程序实现了一个收发一帧10个bit(即无奇偶校验位)的串口控制器,10个bit是1位起始位,8个数据位,1个结束位。 串口的波特律由程序中定义的div_par参数决定,更改该参数可以实现相应的波特率。程序当前设定的div_par 的值 是0x145,对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通 信同步.-EP1C3-uart 1 verilog, implements a program
source
- FPGA串口,verilog HDL串口收发程序-FPGA serial, verilog HDL serial transceiver procedures
uart
- UART的串口程序,收发功能都已实现,直接可用(UART serial procedures, transceiver functions have been achieved, directly available)
teacher_uart
- 由verilog编写的uart收发模块,能够在串口助手发送字符,并在数码管上显示,开发板为basys3 内置约束文件(The UART transceiver module written by Verilog can send characters to serial assistant and display them on the digital tube. the development board is built-in constraint file of basys3)