搜索资源列表
SRAM
- 一个用verilog语言实现的SRAM读写的完整的FPGA工程-A project about sram
QPSKmodulationanddemodulation
- 这是一个QPSK比较完整的FPGA工程,是用Verilog语言写的,主要包括调制解调模块。-This is a QPSK FPGA project is written in Verilog language, including the modem module.
sdram_mdl
- verilog实现SDRAM控制器,quartus工程-verilog SDRAM controller, quartus project
SD_Card_Audio_new
- fpga工程,读取卡上存的音频,verilog,大家分享指正-failed to translate
ccd
- Verilog编写的夏普ccd涉嫌头工程。可在tft上显示采集的视频-failed to translate
Design-exercise-M_sequence
- 通信系统电路设计练习: M序列编码/解码器的设计 作业的背景及训练目的 为了给通信专业的同学们提供一个设计实践的机会,在最短的时间段内掌握数字设计的动手能力,提高Verilog语言的使用能力,所以专门设计了这样一个难度适中的数字通信系统设计练习。本练习是根据工程实际问题提出的,但为了便于同学理解,对设计需求指标做了许多简化。希望同学们在设计范例和老师的指导下,一步一步地达到设计目标。期望同学们能在两至三周内,参考设计范例,独立完成自己的设计任务,在这一过程中学习用Verilog
xulie_100111
- 用verilog语言编写的并且仿真通过的100111序列发生器的工程文件夹-the generator of 100111
addersubtractor
- 用verilog语言编写并通过综合验证的加法减法器的工程目录-the design and implementation of addersubtractor using verilog
calendar
- 这是用Verilog写的万年历,里面包含的日月年各个模块。各个模块用Verilog写的,最后用原理图把各个模块组装成最终的系统。每个模块经过仿真没有问题,整个工程在板子上经过试验,能够完成万年历的功能。-This is the calendar write with Verilog, contains the sun and the moon years each module. Each module in Verilog written, finally the principle diag
uartfifo
- 利用verilog开发的串口FIFO程序,比较基本,包含完整的工程-The verilog developed serial FIFO procedures, more basic, including the complete project
RS232
- 利用verilog开发的串口程序,比较基本,包含完整的工程-Use the verilog development of the serial procedures more basic, including complete engineering
counter
- 利用verilog开发的计数器程序,比较基本,包含完整的工程-Use of the the verilog development of counter program, more basic, including complete engineering
sdram_mdl
- SDRAM的FPGA 工程。用Verilog编写。器件型号为K4S641632,经过实验板验证,绝对可用。-SDRAM FPGA project. Written in Verilog. Device model K4S641632, after the experimental board, absolutely available.
verilogiic1121
- I2C总线的FPGA工程,Verilog编写。是测试过的程序,绝对可用。-I2C bus of the FPGA project, Verilog prepared. Program is tested, absolutely available.
verilogvga
- VGA接口的FPGA工程,Verilog编写,经过测试,绝对可用。-VGA interface of the FPGA project, Verilog prepared, tested, and absolutely available.
lms
- 文件中为lms算法的ise工程,其中包含了lms算法的fpga实现的verilog程序以及testbench,很好的在FPGA上实现了lms算法,还有一些调试程序的总结-Ise project file for lms algorithm, which contains the lms algorithm fpga verilog program to achieve and testbench good lms algorithm implemented on FPGA debugger su
IRDATA
- FPGA接收红外线,Verilog代码,完整的工程-FPGA to receive infrared, Verilog code, complete the project
sdram_mdl
- FPGA控制SDRAM的工程,是用Verilog写的,很好用-FPGA to control the SDRAM project is written in Verilog, easy to use
Tuart_tx_rxh
- 该工程用verilog编写,已通过串口调试助手调试通过,接收模块采采用8倍波特率采样数据,有较好的滤波功能,在PC上完成自发自收功能。 -The project is written in verilog debugging through serial debugging assistant, adopted 8 times the baud rate sampling data receiver module, better filtering done on the PC sponta
FA161_LCD_display
- 联华众科FA161的开发板上实现LCD显示的一个工程文件,编程语言Verilog。可以在LCD上显示按键值。-Lianhua Zhongke FA161 development board LCD display, a project file, programming languages Verilog. The key values can be displayed on the LCD.