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数字频率计实验报告
- 课程设计要求设计并用FPGA实现一个数字频率计,具体设计要求如下: 测量频率范围: 10Hz~100KHz 精度: ΔF / F ≤ ±2 % 系统外部时钟: 1024Hz 测量波形: 方波 Vp-p = 3~5 V 硬件设备:Altera Flex10K10 五位数码管 LED发光二极管 编程语言:Verilog HDL / VHDL-curriculum design and FPGA design to achieve a digital frequency meter,
plj
- 数字频率计 FPGA 用verilog语言编写-Digital Cymometer verilog language used FPGA
verilog
- verilog实现的数字频率计8位数码管输出显示同时矩形波分档输出-verilog implementation of digital frequency meter
gate_control
- verilog写的数字频率计的控制模块,对程序进行控制-written in Verilog digital frequency meter control module, the program control
dispselect
- verilog写的数字频率计的选择模块,用与显示的选择-written in Verilog digital frequency meter option module, used and display options
cpld11245
- 主要介绍了等精度频率测量原理,该原理具有在整个测试频段内保持高精度频率 测量的优点 同时在该原理基础上,采用了Verilog HDL语言设计了高速的等精度测频 模块,并且利用EDA开发平台QUARTUS11 3 .0对CPLD芯片进行写人,实现了计数等 主要逻辑功能 还使用C语言设计了该等精度频率计的主控程序以提高测量精度。本设 计实现了对频率变化范围较大的信号进行频率测量,能够满足高速度、高精度的测频要 求。-Introduced, such as the accuracy
4weishuzipinlvjikongzhimokuai
- Verilog HDL下的4 位数字频率计控制模块源代码-Verilog HDL under four digital frequency meter control module source code
745221frequency
- 用Verilog HDL / VHDL实现的数字频率计(完整实验报告)-Using Verilog HDL/VHDL realization of digital frequency meter (complete test report)
frenquenter
- 等精度频率计设计与文档,有源码,doc格式-Precision frequency meter, etc. The design and documentation, has source code, doc format
verilog
- 完整数字频率计_verilog代码 涉及原理设计实现-Digital Cymometer _verilog complete code relating to the realization of the principle of design, etc.
E_8051_FTEST_K4X4_new
- 是带51单片机核的等精度频率计的FPGA设计的部分。用VHDL编的,也有VERILOG的。-51 is a single chip with precision, such as the nucleus of the frequency of some of FPGA design. VHDL for use as well as the VERILOG.
pinlvji_5
- 用Verilog语言实现的5位频率计设计,为实现功能验证,测频信号是由内部时钟源分频得到,为25KHZ,数据输出为串行输出。使用的硬件资源是altera公司的EPM7218,晶振为40MHZ。-Verilog language used to achieve the five frequency meter design, to achieve functional verification, signal frequency measurement by the internal clock
Verilog-HDL.RAR
- 采用Verilog HDL语言编写的数字频率计,可以作为不错的练习或课设题-vhdl langue
f_meter
- Verilog频率计,可以测出1~9999hz的频率,分模块做成顶层文件-Verilog frequency meter can measure 1 ~ 9999hz frequency, sub-module is made of top-level files
8位数字显示的简易频率计
- (1)能够测试10HZ~10MHZ的方波信号; (2)电路输入的基准时钟为1HZ,要求测量值以8421BCD码形式输出; (3)系统有复位键; (4)采用分层次分模块的方法,用Verilog HDL进行设计,并对各个模块写出测试代码; (5)具体参照说明文档(包含源代码,仿真图,测试波形,详细的设计说明)(A square wave signal capable of testing 10HZ~10MHZ; (2) the reference clock input by the ci
plj
- 2秒闸门时间频率计,以及一个分频器,使用FPGA及verilog语言实现(2 second gate time frequency meter)
Verilog-数字频率计
- verilog数字频率计设计,内容挺详细(Verilog Frequence Measure)
题1:8位数字显示的简易频率计
- 实现巴克码简易频率计,富有代码,功能说明,可以参考(Realize Barker Code Simple Frequency Meter)
frequency
- 用于FPGA开发,使用VERILOG语言编写,并在QUARTUS II仿真平台仿真,实现频率计的功能。(It is used in FPGA development, written in VERILOG language, and simulated on the QUARTUS II simulation platform to realize the function of the frequency meter.)
频率计实验程序代码
- XC7A35TCSG324-1的Verilog频率计程序,支持十分频,支持切换内外信号输入(Verilog frequency meter program of xc7a35tcsg324-1 supports decadal frequency division and switching internal and external signal input)