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Timer_sigtap
- 用Verilog HDL语言写一个计时器。其实就是在计数器的时钟输入端输入一个固定频率的时钟-Verilog HDL language used to write a timer. Is actually counter clock input of a fixed frequency clock input
frequency
- 基于FPGA的verilog语言频率计设计-Design of FPGA-frequency meter
sclock_01
- verilog 秒表,利用视觉暂留,时钟频率-verilog stopwatch
fpga_dds_coylone_2
- dds设计,花了一个星期做的,verilog写的,可生成多种波形,频率范围可上M,性能不错。-dds design, spent a week doing, verilog to write, can generate a variety of waveforms, the frequency range available on the M, the performance good.
src
- 频率综合器 数字控制寄存器 verilog 代码-Digital Frequency Synthesizer Control Register verilog code
sdr
- 全数字OQPSK解调算法的研究及FPGA实现 论文介绍了OQPSK全数字接收解调原理和基于 软件无线电设计思想的全数字接收机的基本结构,详细阐述了当今OQPSK数字 解调中载波频率同步、载波相位同步、时钟同步和数据帧同步的一些常用算法, 并选择了相应算法构建了三种系统级的实现方案。通过MATLAB对解调方案的 仿真和性能分析,确定了FPGA中的系统实现方案。在此基础上,本文采用Verilog HDL硬件描述语言在Altera公司的QuartusⅡ开发平台上设计
instance_f_meter
- 用元件例化的方法实现了频率计的设计,采用的是Verilog语言,实现了较准确的频率测量的功能,最高测量频率可以达到50M左右。-Case of the method of components to achieve a frequency meter design, the use of the Verilog language, to achieve a more accurate frequency measurement function, the maximum measurement
create_pulse
- 使用 verilog hdl 创建指定频率的脉冲-create the fre with verilog hdl
counter
- 本文介绍了基于FPGA的数字频率计的设计方法,设计采用硬件描述语言Verilog ,在软件开发平台ISE上完成,可以在较高速时钟频率(48MHz)下正常工作。该数字频率计采用测频的方法,能准确的测量频率在10Hz到100MHz之间的信号。-This article describes the FPGA-based digital frequency meter design method using hardware descr iption language Verilog, ISE on t
fre_counter
- 用verilog实现的确数字频率计,内部含有各个功能模块-Verilog implementation is actually using digital frequency meter
DDS
- 在MAXPLUSII下开发的基于verilog的直接数字频率合成器-Developed under the MAXPLUSII verilog-based direct digital frequency synthesizer
frequency_measure
- 关于用FPGA测量数字信号源频率的源代码。 用的是verilog语言-Measured using FPGA digital signal on the frequency of the source code. Using verilog language
f_measure_3
- 示波器源程序,由quartus9.1编写,verilog语言支持。采样频率为1M等效采样速率可以到200M-Oscilloscope source code, written by the quartus9.1, verilog language support. Sampling frequency of 1M to 200M equivalent sampling rate can
sixiangzaibosheji
- 本代码采用Altera公司的FPGA为主控芯片,以开发软件QuartusⅡ为工具。采用EDA设计中的自顶向下与层次式设计方法使用精简的DDS算法完成了输入为14MHz,输出四路频率为70MHz的四相序正弦载波(相位分别为0°、90°、180°、270°)的设计。利用Verilog HDL语言进行了程序设计并用QuartusⅡ对设计进行了仿真,验证了其正确性。-DDS algorithm with simplified input for the completion of 14MHz, 70M
freqency
- verilog语言 写的 频率计 ,可在1602液晶上显示,代码齐全,经过验证。-verilog language written in the frequency meter can be displayed on the LCD in 1602, code complete, proven.
plj_book
- EDA,verilog 语言写的频率计,一个是测频,一个是产生一定的频率作为信号源,可在cycloneII 上验证,-EDA, verilog language written in frequency counter, one frequency measurement, one is a certain frequency as the signal source can be verified on the cycloneII, thank you! !
11
- 等精度频率计,verilog语言写的,可在开发板上验证,已经试过-And other precision frequency meter, verilog language, and can be verified on the development board, has tried
DAC_SINE_1K
- 用verilog写的控制da输出信号,输出频率为1khz-Da with verilog write control output signal, the output frequency of 1khz
Cymometer
- 这是本人用verilog语言做的频率计!对于硬件来说是很好的程序.-This is my language to do with verlog frequency counter!
frequence
- 基于verilog语言的频率计,大三的时候写得,我感觉不错哦-Verilog language based on the frequency meter, junior, when written, I feel good, oh