搜索资源列表
Code_for_MedianFilter33.rar
- 3x3中值滤波器的FPGA实现(VERILOG),3x3 median filter FPGA implementation (VERILOG)
MEDIAN.v
- fpga 的 median的verilog实现-median of verilog implementation
medianfilter
- 图像滤波中的中值滤波，有效滤除椒盐噪声，使用verilog语言编写-Image filtering in the median filter, effectively filter out salt and pepper noise, using verilog language
median
- 用verilog编辑的中值滤波器！语言旁表有注释方便理解！-Using Verilog editor median filter! Language beside the table annotated to facilitate understanding!
median_filterCode
- 采用快速中指滤波算法实现图像的中值滤波，使用VHDL语言ISE环境-Image Median Filter
Appendix11
- Median Filter In Verilog
MovingAverageFilter
- This zip file contains the moving average filter code written in verilog HDL
3-3-median-filter
- verilog编写的适用于fpga的3x3模板中值滤波-verilog fpga prepared for the 3x3 median filter template
eetop[1].cn_Code_for_MedianFilter33
- 本程序实现3*3中值滤波的Verilog语言编写-This procedure achieved 3* 3 median filter Verilog language
jf
- verilog编写的alu模块4bit ALU（运算逻辑单元）的设计 给出了此次设计alu的输入输出结构及相应的位数。其中C0是一位的进位输入，A和B分别是4位的数据输入，S0、S1、M分别为一位的功能选择输入信号；Cout是一位的进位输出，F是4为的运算结果输出-Verilog modules prepared by the ALU4bit ALU (arithmetic logic unit) design is given in the design of alu input and ou
3Code_for_Medx
- 3x3中值滤波器的FPGA实现现(VERILOG)可直接使用。 -3x3 median filter FPGA implementation of the present (VERILOG) can be used directly.
median_filter
- 中值滤波的verilog实现，完整工程，调试通过-Median filter verilog achieve complete engineering, debugging through
zhongzhilvbo
- xilinx ise 与modesim联合验证中值滤波 含verilog源程序和整个工程文件-the xilinx ise modesim median filter containing joint verification verilog source, and the entire project file
Midian_fpga
- 图像处理中用到的中值滤波，FPGA实现。verilog语言。-Used in image processing median filter, FPGA implementation. verilog language.
Adder_Array
- 用verilog 实现了一个加法器阵列的计算，32位，位数可以扩展。-Verilog achieved by calculating an adder array 32, the median can be extended.
median
- A median filter in verilog
图像中值滤波FPGA实现V1.0
- 实现图像的中值滤波功能，文件里有效果展示(The realization of the median filter function of the image, the file has the effect of display)
median_filter
- 这个verilog程序实现了图像中值滤波，处理实时性很强，有兴趣的可以参考(This Verilog program implements the median filter in the image, the processing is very real, and the interest can be referred to)
VIP_RAW2RGB2Gray_Medium_Sobel_Erosion_Dilation
- 通过纯HDL逻辑实现,对ov7725摄像头进行图像采集,存储,处理,包括中值滤波,边缘检测等经典图像算法实现(Through the realization of pure HDL logic, image acquisition, storage and processing of ov7725 camera, including median filtering, edge detection and other classic image algorithms.)
module_average_filter
- 一个中值滤波算法的verilog实现。。。。。。。(Verilog implementation of a median filtering algorithm)