搜索资源列表
u-uart
- 一个可综合的串并转换接口verilog源代码-a comprehensive series of conversion and interface Verilog source code
u-uart
- UART verilog TX/RX OpenCores share
bb.rar
- 乒乓结构的verilog程序，风格相当好。大家赶紧 下了啊。,Verilog procedural ping-pong structure, style pretty good. Under the U.S. quickly, ah.
Verilog_UDP
- 辛辛苦苦找到的UDP的资料，在verilog中UDP指的是用户定义的原语。比如说大家有时候会见到“primitive...table...endtable...endendprimitive”这样的代码段，在书上只能找到大概的解释。到网上查的话又老是跟TCP/IP的UDP冲突。所以特地搜集到了这个东西，希望能帮助大家解决“用户原语”相关的问题。-UDP hard to find the information in verilog in the UDP refers to the user-de
DDC
- matlab与synplify DSP AE相结合的DDC实例，希望对大家有所帮助-matlab and synplify DSP AE combining DDC example, in the hope that U.S. help
softdrink
- 自动售货机实现，采用VERILOG语言编写源码，与大家分享，共大家参考-Vending machine implementation, the use of language VERILOG source to share with you a total of U.S. reference
HuaweiFPGAdesignflowguide
- 华为内部的FPGA设计培训教程，详细阐述了设计流程图、Verilog HDL设计、逻辑仿真、逻辑综合。对大家的学习一定有帮助的。-Huawei within the FPGA design training tutorial, a detailed flow chart of the design, Verilog HDL design, logic simulation, logic synthesis. Study of the U.S. must have help.
Fpgamemtest
- 这个是用vhdl语言描写的关于测试FPGA内存的代码。用reset复位，包括.vhdl .ucf .bit文件。我只上传了这3个最重要的。-test memory,including .vhdl .ucf and .bit file~
ASRP
- water marking and verilog vhdl code that related with ham and was very good file for u that understand about water marking
OpenSource_H64
- gl850 usb hub原理图gl850 usb hubgl850 usb hub-gl850 usb hub
VerilogHDL_En
- this is a working draft containing preliminary mate- rial, some of which the reader is likely to nd obscure.-The Verilog Formal Equivalence (VFE) Project is funded by the U.K. Engineering and Physical Sciences Research Council (EPSRC). The Pri
Booths_16bit
- verilog program is there u can download it
IEEE_Standard_verilog_std_1364_1995
- Here is verilog standard which u may find useful! share share
final
- 一个32位的cpu设计，实际是verilog语言，只不过pudn上没有verilog的选项，希望能对你有帮助-this is a 32 bit cpu designer project,which use verilog language. Hope it could help u.
System-Verilog-and-HDL-skills
- 这个教程讲了如何用SystemVerilog写一个CPU，这个教程是和视频专辑http://i.youku.com/u/UMTExNzExOTgw/videos一起使用的，而且里面讲了一些FPGA的逻辑设计技巧-This tutorial about how to use SystemVerilog write a CPU, this tutorial is used in conjunction with, and the video album http://i.youku.com/u/UM
bluetooth_Audio_Codec
- 蓝牙语音的编解码有三种模式：CVSD、A Law、 u Law。本文件实现以上三种编解码方式。其中包括C代码，matlab代码以及verilog代码。-Bluetooth voice codec has three modes: CVSD, A Law, u Law. This file implements the above three codec. Including the C code, matlab code and verilog code
register file generation
- the zip file consist of the verilog code which generate the 32 bit reg file so that u can read and write the data into them
u_pan_yinyue
- verilog程序，可实现从U盘中读取mp3音乐进行播放，同时可在显示屏上显示歌词。-verilog procedures, which are read the U disk mp3 music playback, lyrics can be displayed simultaneously on the screen.
verilog
- 《数字信号处理的FPGA实现（第三版）》作者：U.Meyer-Baese 的配套源码，基于quartus9.0编写，使用的cyclone ii。其中包含FIR IIR FFT等算法的实现，对学习图像处理很有帮助。- FPGA digital signal processing (third edition) Author: U.Meyer-Baese The matching source, based on quartus9.0 preparation, the use of cyc
Final
- u should upload 5 codes/documents