搜索资源列表
ddc_scl_detect
- 显示器ddc数据通道的时钟和数据信号检测的Verilog代码。
DDC.rar
- 个DDC使用的级联滤波器，结构CIC6+CFIR+PFIR,DDC using a cascade filter, the structure of CIC6+ CFIR+ PFIR
DDC_FilterChain_HDL.zip
- simulink demo of ddc,simulink demo of ddc
ddc.rar
- 数字下变频器的matlab实现，一定的设计指标，可以用来知道vhdl程序设计,Digital Down Converter for matlab realized, certain design specifications that can be used to know VHDL Programming
DDC.rar
- verilog语言实现的数字下变频设计。 在ALTERA的QUARTUS ii下实现。实用，好用。,Verilog language implementation of the digital down-conversion design. ALTERA at the implementation of QUARTUS ii. Practical, easy to use.
ddc
- DDC仿真模型，利用systemgenerator实现数字下变频-DDC simulation model, the use of digital down-conversion systemgenerator
DDC_DUC
- 数字上下变频FPGA设计的详细介绍资料，还是中文的。很舍不得上传的哦。-FPGA digital down conversion design detailed information, or Chinese. Oh, very reluctant to upload.
DDC_polyphase
- 自己编写的数字接收机程序，多相信道化接收机MATLAB程序，DDC程序-An DDC program by myself
DDC
- 用6阶CIC实现，加噪声仿真。序内加详尽注释。-6 bands CIC realized, plus noise simulation. Sequence with a detailed note.
DDC
- matlab与synplify DSP AE相结合的DDC实例，希望对大家有所帮助-matlab and synplify DSP AE combining DDC example, in the hope that U.S. help
cic_M
- CIC filter setup, this is special used for the DDC
wddc_module
- 数字下变频的Verilog程序，测试可以直接使用，将A/D信号下变频为基带I，Q两路信号-Digital down conversion of the Verilog program, testing can be used directly to A/D signal down-conversion to baseband I, Q signals two
RealizationofdigitaldownconversionbyFPGA
- 介绍在FPGA 器件上如何实现单通道数字下变频（DDC）系统。利用编写VHDL 程序和调用部分IP 核相结合的方法研究了数字下变频的FPGA 实现方法,并且完成了其主要模块的仿真和调试,并进行初步系统级验证。-Introduced in the FPGA device on how to achieve the single-channel digital down conversion (DDC) system. VHDL procedures and the use of the prepa
verilog_FPGA_DDC
- 这是一个用verilog HDL实现的实现数字下变频的源代码。-This is a verilog HDL used to achieve the realization of digital down conversion of the source code.
GSM_DDC
- GSM中数字下变频器的matlab辅助设计，并可以采用matlab生成verilog代码。-GSM digital down converter in the matlab-aided design, and can be used matlab generate verilog code.
ddc
- 仿真了DDC的工作流程，不了解数字下变频的朋友可以下载-DDC emulation of the workflow, do not understand the digital down-conversion can be downloaded to see if a friend
dspddc_R12p1
- 基于DSPbuilder搭建的DDC，里面包括CIC滤波器，FIR低通滤波器，HB半带滤波器，NCO等，实现了GC5016芯片的功能-DSPbuilder erected based on DDC, which include the CIC filter, FIR low-pass filter, HB half-band filter, NCO, etc. to achieve the function of the GC5016 chip
pci_23
- this is 1553B encoder logic writen in verilog. is compatible with 1553 DDC
Wideband_DDC
- 宽带DDC的Verilog程序，及其MATLAB仿真程序看结果，最大可达100M带宽，程序中用的是50M-Wideband DDC' s Verilog program, and MATLAB simulation program to see the results, the maximum bandwidth of up to 100M, the program used is 50M
DDC中的抽取滤波器设计及FPGA实现
- 本文对下变频模块中抽取滤波进行了详细的分析，并详细阐述了其FPGA的实现过程和方法(In this paper, the decimation filtering in the down conversion module is analyzed in detail, and the realization process and method of FPGA are discussed in detail)