搜索资源列表
mult
- 32位浮点乘法器的源代码，用verilog来实现的-32-bit floating point multiplier source code to achieve with verilog
CourseDesign
- 用Verilog实现一位原码浮点数乘法器，按照累加的方式，逐位相乘，再相加。-Verilog realization of an original code with floating point multiplier, in accordance with the cumulative way, bit by bit multiply, then add.
floating-point-multiplier
- verilog implementation of the floating point multiplier
MULT
- the document used to describe the verilog codes design floating point multiplier in coms design
Floating-Point-Multiplier-in-Verilog
- Floating Point Multiplier in Verilog
Mul32
- Verilog语言编写的单精度浮点数乘法器-The Verilog language of single precision floating point multiplier
altfp_mult_abs
- 浮点数 乘法器带绝对值运算 verilog语言编写 可直接调用-Floating-point multiplier verilog language with absolute operation can be called directly
floating-point-multip
- verilog code for floating point multiplier
基于FPGA的单精度浮点数乘法器设计
- 《基于FPGA的单精度浮点数乘法器设计》详细介绍了按照IEEE754标准在FPGA上实现单精度浮点加减乘除的方法(The design of single precision floating point multiplier based on FPGA introduces in detail the way of realizing single precision floating point addition, subtraction and multiplication and div
Fixed-Floating-Point-Adder-Multiplier-master
- Fixed-Floating-Point-Adder-Multiplier with test bench
float_mult32x32.v
- verilog 语言写的FPGA内部实现硬件浮点乘法器的源码，两个时钟周期完成一次浮点乘法运算(The FPGA language written in Verilog implements the source of the hardware floating point multiplier, and completes the floating point multiplication operation in two clock cycles.)