搜索资源列表
pwm
- 乒乓球实验的VERILOG源代码。XILINX spartan6.-Table Tennis experiment VERILOG source code. XILINX spartan6.
pingpang
- 500分频的verilog源代码。XILINX SPARTAN6.-500 divided by the verilog source code. XILINX SPARTAN6.
vga
- VGA显示的verilog整个代码。在xilinx spartan6板子上测试。-VGA display the verilog source code. Test in on xilinx spartan6 board.
calculator
- 基于赛灵思的spartan-3e开发板的语音智能计算器的设计，开发语言verilog，开发软件ISE，可以根据ucf文件理清引脚关系。应用者需要对开发板和fpga设计有一定的了解！-Development board based on Xilinx spartan-3e voice smart calculator design, development languages Verilog, developing software ISE, according to
led
- verilog编写的分频计数器，控制xilinx板子上led灯-verilog written divider counter control xilinx board led lights
uart
- Code VHDL/Verilog for UART FPGA: Xilinx, Altera-Code VHDL/Verilog for UART FPGA: Xilinx, Altera...
chuot
- code VHDL/ Verilog for Mouser using FPGA: Xilinx, Altera
VGA
- 用verilog写的在xilinx板上经过验证VGA接口程序。非常好用！-Verilog write in the xilinx board proven VGA interface program. Very easy to use!
run_led
- 用verilog写的led跑马灯的程序，在xilinx开发板上经过验证的-Verilog write led Marquee program xilinx development board proven
ps2
- 用verilog写的PS2的程序，在xilinx开发板上经过验证的，非常好用-PS2 program written in verilog in xilinx development board, very easy to use proven
ImageRotate
- 利用verilog实现图像旋转。本程序是基于XILINX公司的ISE实现的。-Verilog image rotation. This procedure is based on XILINX' s ISE.
S8_UART
- FPGA串口Verilog程序，用的芯片是xilinx spantan6-The FPGA serial Verilog the program chip with xilinx spantan6
zynq_base_trd_14_3
- xilinx的视频处理参考Verilog代码-Video Targeted Reference Design On Xilinx FPGA With Verilog
carry_select
- 上传的代码是基于Xilinx下的ISE开发平台，用Verilog语言编写的carry_select加法器。-Upload the code is based on the Xilinx ISE development platform, the the Verilog language of carry_select adder.
music
- 利用FPGA模拟弹钢琴的Verilog代码。在Xilinx ISE 14.3 编译通过-Using FPGA Verilog code simulation play the piano. Compiled by Xilinx ISE 14.3
EMAC6
- verilog实现的FPGA三态以太网链路层通信代码，里面有状态机，并按各个模块的功能分了文件夹，还有说明文档，自定义帧的产生和接收，开发环境为Xilinx ISE，测试无误。-verilog realization FPGA Tri-Mode Ethernet link layer communication code, which the state machine, according to the function of each module sub folder, as well a
chunge
- Xilinx FPGA verilog 数字钟-Xilinx FPGA verilog digital clock
Virtex-5-FPGA-Data-Sheet
- 本程序基于xilinx fpga，v5，verilog语言，主要用于数据采集，采集频率可达500m，通过pingpang缓存进行数据转发。-The program xilinx fpga, v5, verilog language, mainly used for data acquisition, acquisition frequency of up to 500m, through data forwarding pingpang cache.
code
- 32位全加器 使用verilog写的硬件描述语言，xilinx芯片上运行过-32bits full adder
code
- 32bits流水线加法器，verilog语言的，xilinx公司芯片上运行通过-The 32bits pipelined adder verilog language, xilinx chip run through