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subr
- VHDL 8位无符号除法器 试验报告 计算前在A和B端口输入被除数和除数,然后在Load线上送高电平,把数据存到除法计算电路内部,然后经过若干个时钟周期,计算出商和余数,并在C和D端输出。 其实现方法是,将除法器分为两个状态:等待状态与运算状态。 开始时除法器处于等待状态,在该状态,在每一时钟上升沿,采样Load信号线,若是低电平,则仍处于等待状态,如果采样到高电平,除法器读取A,B数据线上的输入数据,保存到内部寄存器a_r,b_r,置c_r为0,d_r为a_r,判断除数是否为零,若
200632146671689
- 基于vhdl在FPGA中实现高精度快速除法-based on the FPGA VHDL precision rapid division
baweichufaqi
- 介绍了利用VHDL实现八位除法,采用层次化设计,该除法器采用了VHDL的混合输入方式,将除法器分成若干个子模块后,对各个子模块分别设计,各自生成功能模块完成整体设计,实现了任意八位无符号数的除法。 -Introduced the use of VHDL to achieve eight division, the use of hierarchical design, the divider using VHDL mixed-input methods, will be divided in
ps
- RS(204,188)译码器的设计 异步FIFO设计 伪随即序列应用设计 CORDIC数字计算机的设计 CIC的设计 除法器的设计 加罗华域的乘法器设计-RS (204188) decoder design of asynchronous FIFO design application design sequence was pseudo-CORDIC design of digital computer design CIC divider design Le Hua
chufa
- 使用VHDL编写的除法程序,当然是采用的分数形式,小数点的除法还没有实现。-Division programs written using VHDL, of course, use the Fraction, decimal point of division has not been achieved.
vhdlchufaqi
- 这是一个基于VHDL语言的bch除法器,其功能就是实现二进制除法,采用移位的方式进行-This is based on VHDL language bch divider, its function is to achieve binary division, the way by shift
divid
- 基于VHDL的divided建模,方便调用,主要是除法运算,用于数据移位-Divided modeling based on VHDL, call the main division operation is used to shift data
Divider
- 除法的fpga实现 开发环境ise 语言vhdl-divider ise vhdl fpga
chufa
- 用VHDL设计的四位除法器,可以实现四位二进制数的除法操作-Four divider with VHDL design, you can achieve the four binary division operation
jianyijisuanqi
- 用VHDL实现简易计算器,实现加法、减法、乘法、除法的功能。-Use VHDL to realize simple calculator, can realize the function of addition, subtraction, multiplication, and division.
zhaoyueyue2xiugai
- 4位有符号数除法,vhdl语言编译,可实现有符号数的除法-4 signed division
Divider
- xilinx 除法ip核调用 含测试程序 vhdl语言-xilinx ip nuclear division calls including test procedures vhdl language
third
- 用VHDL语言实现了一个有符号除法的程序,用移位相减实现。-Just like
fu_dian_chu_fa
- VHDL浮点除法运算,VHDL浮点数除法,源码,含仿真图 -VHDL floating point division, source code, including simulation mapVHDL floating point division, source code, including simulation map
code
- 本源码是基于VHDL语言环境下的基础实验源码,共分七个部分。分别是:序列检测器、数字密码锁、四位有符号数除法、同步FIFO、DPLL的设计以及Cordic 算法实现。对于VHDL的初学者具有极大的参考价值。-The source is based on experimental basis source VHDL language environment, it is divided into seven sections. They are: the sequence detector, di
Fau
- 使用vhdl写的32位 64位浮点数加法模块、浮点数乘法模块、浮点数除法模块(Use vhdl write 32-bit 64bit floating-point addition module, floating-point multiplication module, floating-point division module)