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dds正弦发生器代码
- 讲述了dds直接数字频率合成的基本原理，同时用ＶＨＤＬ语言编写dds原代码用于生成正弦波，并在ISE开发平台进行仿真和MATLAB验证正弦波输出结果-described dds direct digital frequency synthesis of the basic tenets addition to the use of VHDL prepared dds source used to produce sine, and ISE development platform for sim
dds
- verilog 硬件语言实现DDS，使用ise11.1和modelsim se6.5仿真测试-verilog hardware language DDS, using the simulation test ise11.1 and modelsim se6.5
MD_DDS_10bit_VHDL
- 十位DA输出的DDS，用VHDL实现，环境：ISE 8.1，仿真软件：ModelSim_SE_6.1b-10 DA output of the DDS, with the VHDL implementation, environment: ISE 8.1, simulation software: ModelSim_SE_6.1b
FPGAdesignandFIRimplementation
- 文档中含有DDS的VHDL实现，FIR滤波器串并FPGA实现，synplify,ISE,ModelSim后仿真流程和FPGA设计的资料-document contains DDS implementation with VHDL , FIR filter serial to parallel and FPGA implementation, and synplify, ISE, ModelSim simulation and FPGA design
test3
- DDS 100MHZ to 4MHZ este DDS esta reado con ISE NAvigator en lenguage VHDL, funciona pero hay diferencias con la cantidad de muestras para crear la onda senoidal, se recomienda aunmentar el numero de muestras para lograr una mejor exactitud de la on