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experiment8_only1
- 交通灯实验程序，集成在一个工程里面，VHDL语言编写。我们上课的作业-Traffic lights test procedures, integration in a project which, VHDL language. We are working class
uart_read_send
- uart自收发的vhdl实现,包括quartus工程文件及modelsim仿真工程文件(调试通过)-uart vhdl from the transceiver to achieve, including the quartus project file and modelsim simulation project file (debugged)
LCD_DISPLAY
- lcd显示的VHDL实验,包括quartus工程文件及modelsim仿真文件-lcd display VHDL experiments, including the quartus project file and modelsim simulation file
viterbi_encoding_213
- Viterbi213编码程序的VHDL的实现，包括整个quartusII 的工程文件，以及仿真波形图-Viterbi213 VHDL code implementation of procedures, including the quartusII project files, and simulation waveforms
Spread_Frequency
- spearding freqeuncy project by vhdl code
Checkers
- Checkers is one of the most commonly played games in the world, each culture has its own version of it and feels as if it originated from it, though its original implementation was Chinese. This project is interesting for several reasons including th
tiaozhijietiaoqi
- 调制解调器（全数字）vhdl程序，包含工程文件可直接编译-Modem (digital) vhdl program, including project files can be directly compiled
fir_filter
- 采用vhdl语言在Altera的开发板DE2-70上实现的低通滤波器的工程-Vhdl language used in the Altera DE2-70 development board to achieve the low-pass filter project
I2C-BusDesign
- 本程序给出了完整的I2C设计工程文件及VHDL源代码-This procedure gives the complete design of the project file and I2C VHDL source code
8255_VHDL_source
- 基于quartusII的8255设计方案，采用硬件描述语言VHDL描述，很好的实现了8255通用接口芯片的设计-a project about 8255 chip based on quartusII,discr ipted by vhdl
lowpowerfir
- This project was undertaken to produce a low power FIR filter for inclusion in a VHDL target library. The design was completed using OrCAD s Capture CIS, from this the VHDL code has been extracted. This method has allowed complete testing of the syst
B_to_D
- 二进制转BCD码程序，可作为7段数码管显示的编解码程序，VHDL编写的FPGA工程。-BCD binary code change process, as 7 digital display codec process, VHDL FPGA project prepared.
cont10_v.sym
- 十进制计数器既可采用QuartusII的宏元件74160，也可用VHDL语言设计。在项目编译仿真成功后，将设计的十进制计数器电路设置成可调用的元件cont10_v.sym，用于4位十进制计数器的顶层设计。-Decimal counter can use QuartusII macro components 74160, also available VHDL language design. After the success of the project compiled simulation
dianzizhong
- 该代码是用VHDL编写的电子时钟，可以实现调时调分，7段码显示，在Xilinx的Spartan3E上下载测试过，压缩文件中包含了整个工程，并有管脚分配文件，非常适合VHDL的初学者，比如一些基本的按键，去抖，闪烁写法。-The VHDL code is written using the electronic clock adjustment can be achieved when the transfer points, 7 code shown to download the Xilinx
display_fsm
- 采用状态机移位显示字符的VHDL代码，包括QUARTUS2的完整工程。-Shifting display with state machine . VHDL code , including the complete QUARTUS2 project.
qiangda
- 设计的四人多路抢答器，基于vhdl开发环境-this project is based on vhdl
SIREN
- An Alarm Project Writen in VHDL for FPGA Devices
lift
- 本课题要求设计一个电梯控制系统，传统的电梯控制系统仅仅要求实现对一栋电梯的控制，而本题要求设计一个实现两栋电梯联动的基于VHDL的电梯控制系统。具体要求如下： 需要大楼为4层，2部电梯，每部电梯内部都有如下按键：1-4楼的按键选择，开门键，关门键，报警键。每部电梯的每层楼外面都有上楼键和下楼键（1楼只有上楼键，六楼只有下楼键）。电梯的设计参照日常生活中电梯实际运行规律设计。 两部电梯之间互相联动，即同时按下任何一部电梯的外部向上或向下键之后，两部电梯同时接受此指令，然后由系统判断，与该请求所
registrationform
- REGISTRATION FORM FOR VHDL VLSI COURSE WITH PROJECT MINOR AND MAJOR USE FOR SUMMER TRAINING AND WEEKLY VHDL PROGRAMMING.
odometre
- Student project in VHDL Platform Xilinx about odometry