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xapp852.zip
- Xilinx Virtex5 for RLDRAM design,Xapp852 (Xilinx Design RLDRAM II Memory Interface for Virtex-5 FPGAs)
PipelineCPU
- 设计一个32位流水线MIPS微处理器，具体要求如下： 1. 至少运行下列MIPS32指令。 ①算术运算指令：ADD、ADDU、SUB、SUBU、ADDI、ADDIU。 ②逻辑运算指令：AND、OR、NOR、XOR、ANDI、ORI、XORI、SLT、SLTU、SLTI、SLTIU。 ③移位指令：SLL、SLLV、SRL、SRLV、SRA。 ④条件分支指令：BEQ、BNE、BGEZ、BGTZ、BLEZ、BLTZ。 ⑤无条件跳转指令：J、JR。 ⑥数据传送指令：LW、SW
Asynchronous_FIFO
- 异步FIFO代码，虽然是一个比较简单的程序，但有助于我们更好的理解异步FIFO-This implementation is based on the article Asynchronous FIFO in Virtex-II FPGAs writen by Peter Alfke. This TechXclusive Xilinx website. It has some minor modifications.
verilog-radix4
- Master Thesis(FFT_RADIX-4)-This thesis deals with a 64-point Radix-4 in-place FFT, based on an improved FFT algorithm. The whole FFT structure was implemented based on self-designed modules and by manipulating the embedded Virtex II FPGA’s module
DES_Triple-DES-IP-Cores
- Triple DES 密码算法。 利用Xillinx公司的Virtex-II芯片测试了。正常动作。-Triple DES core implementation in verilog. It takes three standard 56 bit keys and 64 bits of data as input and generates a 64 bit encrypted/decrypted result.
wenbenxianshi
- 用modelsim和ise开发文本显示系统。包括键盘PS2输入，SVGA视频同步，RGB处理，作者姓名显示，光标发生，图片动态显示。采用XUP Virtex-II Pro开发系统。-With modelsim and ise development text display system.Including the PS2 keyboard input, SVGA video synchronization, RGB, author name, according to the cursor,
ddr_sdr
- DDR SDRAM Controller Core - has been designed for use in XILINX Virtex II FPGAs - works with DDR SDRAM Device MT46V16M16 without changes - may be easily adapted to any other DDR SDRAM device-DDR SDRAM Controller Core - has been designe
xapp223
- UART Receiver with internal 16-byte buffer and UART Transmitter with internal 16-byte buffer for Virtex, Virtex-E and Spartan-II FPGAs-UART Receiver with internal 16-byte buffer and UART Transmitter with internal 16-byte buf
ddr_sdram
- 包含ddr_sdr_conf_pkg.vhd，reset.vhd，ddr_dcm.vhd，user_if.vhd，ddr_sdram.vhd，Mt46v16m16.vhd以及仿真TB文件；设计采用Virtex ii系列芯片，DDR_SDRAM型号为Mt46v16m16，可用于进行DDR控制的初步学习使用；通过细致了解并进行逻辑控制，可深入理解DDR芯片内部构造； 支持133MHz系统时钟频率，突发长度为2，可进行读、写、NOP、激活、自刷新配置、预充电以及各ROW/BANK的激活改变等动作，较