搜索资源列表
Wishbone
- wishbone总线协议详细的技术说明文挡！-wishbone bus protocol detailed technical descr iption of the text block!
wishbone_VHDL.rar
- wishbone总线的VHDL源代码 wishbone适用于与FPGA中IP核的高速通信，其接口简单，速度快 成为ip通信的主流,Wishbone Bus VHDL source code Wishbone applicable to IP core in FPGA high-speed communications, and its easy interface, fast becoming the mainstream of ip communications
wb_lpc_latest.tar.gz
- Wishbone to LPC (Low-Pin Count) Bridge, includes master and slave modules. Supports 8-bit I/O Read and Write cycles, 8-bit Memory Read/Write cycles, DMA cycles, and up to 32-bit Firmware memory read/write cycles. Serial IRQ support is also provided.
SDCard_Controller.rar
- SD卡控制器IP. 兼容SD卡协议2.0。与wishbone bus 接口，方便与其他IP连接使用。 ,SD Card Controller IP. Compatible with SD Card Agreement 2.0. With the wishbone bus interface to facilitate the use of other IP connections.
pci.tar.gz 完成WB BUS和PCI bus之间的传输
- verilog编写的PCI总线，提供了Wishbone bus和PCI local bus之间的接口，内由两个独立的模块组成，分别完成WB BUS和PCI bus之间的传输,The PCI IP core (PCI bridge) provides an interface between the WISHBONE SoC bus and the PCI local bus. It consists of two independent units, one handling transact
wbspec_b4
- wishbone总线的规范介绍，很详细，很不错-wishbone bus specification describes, in great detail, very good
uart16550
- uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can b
SoCWishboneSystem
- SoC-Wishbone System IP核的VHDL语言源代码-SoC-Wishbone System IP core language VHDL source code
wishbone_i2c_master_vhd
- wishbone i2c master vhdl code
spi_wishbone
- spi wishbone bus code
uart
- uart协议、实现、验证，基于wishbone协议，工业标准为16550A-UART protocol, implementation, verification, based on the Wishbone protocol, the industry standard for the 16550A
ethernet.tar
- VHDL MAC wishbone VHDL MAC wishbone-VHDL MACVHDL MAC wishbone VHDL MAC wishbone
ahb2wishbone_latest.tar
- opencore ahb to wishbone bus verilog code
pit_latest.tar
- Programmable Interval Timer: Overview Category :: Other Language :: Verilog Development status :: Beta WishBone Compliant :: Yes Phazes :: Design done, Specification done
ima_adpcm_encoder_latest.tar
- This project features a full-hardware sound compressor using the well known algorithm: IMA ADPCM. The core acts as a slave WISHBONE device. The output is perfectly compatible with any sound player with the IMA ADPCM codec (included by defau
camera_up
- Camera Interface模块是视频输入转换存储模块。该模块一端接通用的video camera设备，另一端接AHB总线。实现了将Camera捕捉到的数据进行转换、并通过DMA存储到memory中。该IP支持ITU-R BT 601/656 8-bit 模式。支持YCbCr, RGB格式输入。可以将camera产生的YCbCr信号转换成24bit RGB 信号，然后下采样生成16bit RGB 5：6：5的LCD能直接读取显示的数据。该设备支持图像的镜像和翻转，以便适应手持式设备在移动环境
spi_master
- SPI wishbone master and verification environment
wb_dma
- wishbone接口dma控制器，适合于构建soc系统，特别适用于视频开发-dma controller with wishbone interface，fitting for soc design，especially for video development.
i2c
- 基于wishbone总线的I2C的ip核，可供学习和参考．-I2C Bus-based wishbone of ip core, available for study and reference.
wishbone
- wishbone IP CORE Verilog quartus-wishbone IP CORE Verilog quartusii