搜索资源列表
singleTcpu
- 单周期cpu设计,基于xilinx ISE环境设计,使用MIPS语言-Single cycle, the CPU is designed, based on xilinx ISE environment design, the use of MIPS language
wiznet5500_Verilog
- 使用Xilinx Spartan-6 XC6SLX9的FPGA驱动Wiznet5500网卡芯片的Verilog设计,可以发送和接收,已经测试,无误。-Using the Xilinx Spartan-6 XC6SLX9 FPGA driver The Wiznet5500 network card chip Verilog design can be sent and received, has been tested, and is correct.
SHORT_TRAINING
- 基于XILINX FPGA的OFDM通信系统基带设计之短训练序列模块源码-Baseband OFDM communication system design based on XILINX FPGA module source of short training sequence
Planahead
- Xilinx FPGA设计软件Planahead的设计方法,包括GUI界面操作,脚本命令操作,常用问题解答,适合初学者自学。-Xilinx FPGA design software Planahead design methods, including GUI interface operation, scr ipt command operation, commonly used questions, suitable for beginners self-study.
xapp800
- XAPP800SPICPLD源码参考设计-THIS DESIGN IS PROVIDED TO YOU AS IS . XILINX MAKES AND YOU RECEIVE NO WARRANTIES OR CONDITIONS, EXPRESS, IMPLIED, STATUTORY OR OTHERWISE, AND XILINX SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGE
scan_key_4x4_1602
- 基于xilinx的fpga4x4矩阵键盘输入lcd1602显示矩阵键盘输入代码,模块化设计,程序易移植-Based on xilinx fpga4x4 matrix keyboard input lcd1602 display matrix keyboard input code, modular design, easy to transplant program
XPS_EMC
- Xilinx 公司 nor flash控制器接口,使用EDK搭建工程完成设计(Xilinx EDK XPS EMC NOR FLASH INTERFACE)
pll_test
- PLL,即锁相环。是FPGA中的重要资源。由于一个复杂的FPGA系统往往需要多个不同频率,相位的时钟信号。所以,一个FPGA芯片中PLL的数量是衡量FPGA芯片能力的重要指标。FPGA的设计中,时钟系统的FPGA高速的设计极其重要,一个低抖动, 低延迟的系统时钟会增加FPGA设计的成功率。本例程调用Xilinx提供的PLL核来产生不同频率的时钟, 并把其中的一个时钟输出到FPGA外部IO上, 也就是开发板的SMA接口上。(PLL, pll. It's an important resource
Xilinx新一代FPGA设计套件Vivado配套资料
- verilog经典教程,入门者的必选书籍,非常实用,可以学习到很多的知识(verilog classic tutorial, entry must be books, very practical, you can learn a lot of knowledge)
lcd显示驱动
- 了解LCD驱动原理;使用Xilinx Starter3E 开发板;在开发板LCD上显示“EDA课程设计 学生姓名xxx 学号xxx”字样,有循环显示和移动功能。(Understand the principle of LCD driver; Use Xilinx Starter3E development board; On the development board LCD display "EDA curriculum design student name xxx student
15010120041_高瑞雪_lab2
- 在本实验中,将使用System Generator for DSP创建一个带乘法器和累加器的12-bit x 8-bit MAC(Multiplier Accumulator),并使用System Generator 的Resource Estimator块来估计资源利用率。 在仿真Simulink中的设计之后,将从该设计中生成VHDL代码和内核,并在Xilinx ISE Foundation开发软件中实现MAC。(Design, construct and verify the specifi
virtex7_pcie_dma_latest.tar
- PCIE_dma 设计,基于xilinx virtex7 fpga芯片,实现高速传输(PCIE_dma design, based on the Xilinx virtex7 FPGA chip, to achieve high speed transmission)
ug835-vivado-tcl-commands
- Vivado是Xilinx最新的FPGA设计工具,支持7系列以后的FPGA及Zynq 7000的开发。与之前的ISE设计套件相比,Vivado可以说是全新设计的。无论从界面、设置、算法,还是从对使用者思路的要求,都是全新的。看在Vivado上,Tcl已经成为唯一支持的脚本,此文件是vivado是tcl命令的集合。(Vivado is Xilinx's latest FPGA design tool that supports development of FPGAs and Zynq 7000s
E4_6_FirIpCore
- 用vhdl语言在xilinx上用ip核实现的fir滤波器的设计(Design of FIR filter implemented with IP kernel on Xilinx in VHDL language)
i2c
- zynq iic测试,IIC EEPROM接口测试程序,Xilinx参考设计(zynq iic test,The following example shows adding the I2C EEPROM for the ML507 to it's device tree. The value of 0x050 is the I2C address of the EEPROM.)