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7seg_led
- 使用xilinx公司的FPGA实现了七段码的定时器时钟程序-use of the Xilinx FPGA in paragraph 107 of the Code timer clock procedures
61EDA_D408
- 跑表计时器 用xilinx里的各种软件都实现了一遍-Stopwatch timer with Xilinx
timer
- This application is about the Timer in the Xilinx FPGA. It suits students in the college who have little knowlege about the FPGA.
vhdl
- 基于PicoBlaze的实时时钟设计。PicoBlaze是Xilinx的8位软核。采用汇编语言编写。-Uart real timer
shuzibiao
- xilinx下使用vhdl编写数字表 具有启动、复位、暂停、暂停后继续计时等功能 能显示的秒计数时间精确到小数点后第二位，即能显示**.**s -xilinx vhdl prepared using digital watch with a start, reset, pause, pause, continue after the timer function can display the seconds counting time accurate to the second
MyDigiditClock2
- 一个简单的基于赛灵思公司的nexys3的秒表计时器。能够实现计时的开始、暂停、复位、切换显示百分秒。无需连接任何其他的硬件。-Based on a simple Xilinx nexys3 stopwatch timer. Start timing can be achieved, pause, reset, switch the display percentile seconds. Without connecting any additional hardware.
Timer
- 基于verilog xilinx spartan 3e100的秒表计时器-Based verilog xilinx spartan 3e100 stopwatch timer